XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 39
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XR16V794IV-0B-EVB
Manufacturer Part Number
XR16V794IV-0B-EVB
Description
Supports V794 64 Ld TQFP,ISA Interface
Manufacturer
Exar Corporation
Datasheet
1.XR16V794IV-F.pdf
(53 pages)
Specifications of XR16V794IV-0B-EVB
Design Resources
XR17V798/794 Eval Board Schematic
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REV. 1.0.1
Enhanced features are enabled or disabled using this register. Bits 3:0 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
•
•
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
•
•
4.13
Logic 0 = Automatic CTS/DSR flow control is disabled (default).
Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is
through MCR bit-2.
Logic 0 = Automatic RTS/DTR flow control is disabled (default).
Logic 1 = Enable Automatic RTS/DTR flow control.
Enhanced Feature Register (EFR) - Read/Write
FCTR B
T
ABLE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IT
-3
17: 16 S
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
FCTR B
ELECTABLE
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
IT
-2
H
YSTERESIS
FCTR B
Table 18
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IT
L
-1
EVELS
39
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
W
FCTR B
HEN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
T
RIGGER
IT
-0
T
ABLE
RTS/DTR H
-D
(
CHARACTERS
IS
S
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
+/- 4
+/- 6
+/- 8
+/- 8
ELECTED
0
YSTERESIS
XR16V794
)