ISP1507ABSTM STEricsson, ISP1507ABSTM Datasheet - Page 56

• Manufacturer Part Number: ISP1507ABSTM
• Manufacturer: STEricsson

Specifications of ISP1507ABSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Table 38.
Table 39.
Table 40.
Table 41.
Legend: * reset value
CD00222689
Product data sheet
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Symbol
SCRATCH
[7:0]
Symbol
-
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
Symbol
-
LINESTATE1
LINESTATE0
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
10.1.10 SCRATCH register
10.1.12 Access extended register set
10.1.11 Reserved
10.1.9 DEBUG register
R
7
0
Access
R/W/S/C 00h*
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes; see
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Description
reserved
Line State 1: Contains the current value of LINESTATE 1.
Line State 0: Contains the current value of LINESTATE 0.
Description
reserved
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
Value Description
R
6
0
Valid Latch: Automatically set when an unmasked event occurs on A_VBUS_VLD.
Scratch: This is an empty register byte for testing purposes. Software can read,
write, set and clear this register. The functionality of the PHY will not be affected.
R
5
0
reserved
Rev. 04 — 20 May 2010
R
4
0
R
3
0
ISP1507A; ISP1507B
Table
Table
41.
ULPI HS USB OTG transceiver
R
39. This register indicates the
2
0
STATE1
© ST-ERICSSON 2010. All rights reserved.
LINE
R
1
0
STATE0
LINE
R
0
0
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