ISP1562BE STEricsson, ISP1562BE Datasheet

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ISP1562BE

Manufacturer Part Number
ISP1562BE
Description
Manufacturer
STEricsson
Datasheet

Specifications of ISP1562BE

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
LQFP
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Dear customer,
As from August 2
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
Company name - NXP B.V. is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site -
Contact information - the list of sales offices previously obtained by sending
an email to
under Contacts.
http://www.nxp.com
salesaddresses@nxp.com
nd
2008, the wireless operations of NXP have moved to a new company,
IMPORTANT NOTICE
is replaced with
, is now found at
http://www.stnwireless.com
http://www.stnwireless.com
www.stnwireless.com

Related parts for ISP1562BE

ISP1562BE Summary of contents

Page 1

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

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ISP1562 Hi-Speed USB PCI host controller Rev. 03 — 14 November 2008 1. General description The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) host controller. It integrates two Original USB Open Host Controller Interface (OHCI) ...

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... Set-Top Box (STB) I Web appliances 4. Ordering information Table 1. Ordering information Type number Package Name Description ISP1562BE LQFP100 plastic low profile quad flat package; 100 leads; body 14 ISP1562_3 Product data sheet and V aux(3V3) Rev. 03 — 14 November 2008 ISP1562 HS USB PCI host controller ...

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PME# 99 PCICLK 22, 32 AD[31: 31, 33, 34 54, 56, 57, PCI CORE 59, 62, 63 C/BE#[3:0] 23, 35, 48, 60 REQ# 9 PCI MASTER ...

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... I(VREG3V3) GNDA 17 18 REG1V8 GNDD 19 AD[26] 20 AD[25 AD[24] C/BE#[3] 23 IDSEL CC(I/O) Fig 2. Pin configuration ISP1562_3 Product data sheet ISP1562BE Rev. 03 — 14 November 2008 ISP1562 HS USB PCI host controller 75 XTAL2 74 XTAL1 73 AUX1V8 72 GNDA 71 V CC(I/O) 70 AD[0] 69 AD[1] 68 AD[2] 67 AD[3] 66 AD[4] ...

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NXP Semiconductors 6.2 Pin description Table 2. Symbol GNDA AUX1V8 V I(VAUX3V3) INTA# RST# GNDD PCICLK GNT# REQ# AD[31] V CC(I/O) AD[30] AD[29] AD[28] AD[27] V I(VREG3V3) GNDA REG1V8 GNDD AD[26] AD[25] AD[24] ISP1562_3 Product data sheet Pin description [1] ...

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NXP Semiconductors Table 2. Symbol C/BE#[3] IDSEL V CC(I/O) AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] GNDD AD[17] AD[16] C/BE#[2] FRAME# IRDY# TRDY# DEVSEL# V CC(I/O) STOP# CLKRUN# ISP1562_3 Product data sheet Pin description …continued [1] Pin Type Description 23 I/O ...

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NXP Semiconductors Table 2. Symbol REG1V8 PERR# SERR# GNDA PAR C/BE#[1] GNDD AD[15] AD[14] AD[13] AD[12] AD[11] V CC(I/O) AD[10] AD[9] REG1V8 AD[8] C/BE#[0] GNDA AD[7] AD[6] ISP1562_3 Product data sheet Pin description …continued [1] Pin Type Description 43 - ...

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NXP Semiconductors Table 2. Symbol GNDD AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] V CC(I/O) GNDA AUX1V8 XTAL1 XTAL2 GNDD V CC(I/O)_AUX OC1_N PWE1_N GNDA RREF GNDA DM1 GNDA DP1 V DDA_AUX OC2_N PWE2_N GNDA ISP1562_3 Product data sheet Pin description ...

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NXP Semiconductors Table 2. Symbol DM2 GNDA DP2 V DDA_AUX GNDD GNDD SCL SDA V CC(I/O)_AUX PME# V CC(I/O)_AUX [1] Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol names ending with underscore ...

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NXP Semiconductors 7. Functional description 7.1 OHCI host controller An OHCI host controller per port transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI host controller The EHCI host controller ...

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NXP Semiconductors 7.7 Power-On Reset (POR) Figure 3 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops ensure that the ...

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NXP Semiconductors ( (2) This electrolytic or tantalum capacitor must be of LOW ESR type (0.2 (3) In ISP1562_1 data sheet, the electrolytic or tantalum capacitor value was mentioned This Fig 4. 8. PCI 8.1 ...

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NXP Semiconductors signal INTA#. These functions provide memory-mapped, addressable operational registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . Each function has its ...

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NXP Semiconductors Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI Address Bits Bits PCI configuration header registers 00h DID[15:0] 04h STATUS[15:0] 08h CC[23:0] 0Ch reserved HT[7:0] 10h 14h 18h 1Ch 20h ...

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NXP Semiconductors Table 4. VID - Vendor ID register (address 00h) bit description Legend: * reset value Bit Symbol Access Value VID[15:0] R 8.2.1.2 Device ID register This is a 2-byte read-only register that identifies a particular ...

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NXP Semiconductors Table 7. CMD - Command register (address 04h) bit description Bit Symbol Description reserved - 9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back transactions to various devices. The ...

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NXP Semiconductors 8.2.1.4 Status register The Status register is a 2-byte read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8. STATUS - Status register (address 06h) bit allocation Bit 15 Symbol DPE ...

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NXP Semiconductors Table 9. STATUS - Status register (address 06h) bit description Bit Symbol Description 5 66MC 66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz. 0 — 33 MHz 1 — ...

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NXP Semiconductors Table 12 Class Code register (address 09h) bit description Bit Symbol Description BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller. 15 ...

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NXP Semiconductors Table 16 Header Type register (address 0Eh) bit description Bit Symbol Description 7 MFD Multi-Function Device: This bit identifies a multifunction device. 0 — The device has single function. 1 — The device has multiple functions. ...

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NXP Semiconductors Table 19. SID - Subsystem ID register (address 2Eh) bit description Legend: * reset value Bit Symbol Access SID[15: 1561h for OHCI1 and OHCI2 1562h for EHCI. 8.2.1.13 Capabilities ...

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NXP Semiconductors 8.2.1.16 MIN_GNT and MAX_LAT registers The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value specifies a period of time ...

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NXP Semiconductors 8.2.2 Enhanced host controller-specific PCI registers In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB ...

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NXP Semiconductors Table 29. FLADJ value 0 (00h) 1 (01h) 2 (02h (1Fh) 32 (20h (3Eh) 63 (3Fh) 8.2.2.3 PORTWAKECAP register Port Wake Capability (PORTWAKECAP 2-byte register used to establish a policy about which ...

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NXP Semiconductors Table 32. CAP_ID - Capability Identifier register bit description Address: Value read from address 34h + 0h Legend: * reset value Bit Symbol Access CAP_ID[7:0] R 8.2.3.2 NEXT_ITEM_PTR register The Next Item Pointer (NEXT_ITEM_PTR) register ...

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NXP Semiconductors Table 35. PMC - Power Management Capabilities register bit description Address: Value read from address 34h + 2h Bit Symbol Description PME_S PME Support: These bits indicate the power states in which the function may ...

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NXP Semiconductors 8.2.3.4 PMCSR register The Power Management Control/Status (PMCSR) register is a 2-byte register used to manage the power management state of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation ...

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NXP Semiconductors Table 37. PMCSR - Power Management Control/Status register bit description Address: Value read from address 34h + 4h Bit Symbol Description PS[1:0] Power State: This two-bit field is used to determine the current power state ...

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NXP Semiconductors Table 40. Originating device’s bridge PM state D2 D3 hot D3 cold 8.2.3.6 Data register The Data register is an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as ...

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NXP Semiconductors C-bus interface A simple I product ID and some other configuration bits from an external EEPROM. 2 The I C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and ...

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NXP Semiconductors The slave address that the ISP1562 uses to access the EEPROM is 101 0000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information ...

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NXP Semiconductors 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating ...

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NXP Semiconductors Table 42. USB host controller registers Address OHCI register 4Ch HcRhDescriptorB 50h HcRhStatus 54h HcRhPortStatus[1] 58h HcRhPortStatus[2] 5Ch reserved 60h reserved 64h reserved 68h reserved 6Ch reserved 70h reserved [1] Reset values that are highlighted, for example, 0, ...

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NXP Semiconductors Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access R Table 44. HcRevision - Host Controller Revision register bit description Address: Content of the base address register + 00h Bit Symbol Description 31 to ...

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NXP Semiconductors Table 46. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit Symbol Description reserved - 10 RWE Remote Wake-up Enable: This bit is used by the ...

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NXP Semiconductors Table 46. HcControl - Host Controller Control register bit description Address: Content of the base address register + 04h Bit Symbol Description CBSR Control Bulk Service Ratio: This specifies the service ratio of control EDs ...

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NXP Semiconductors Table 48. HcCommandStatus - Host Controller Command Status register bit description Address: Content of the base address register + 08h Bit Symbol Description reserved - SOC[1:0] Scheduling Overrun Count: The bit is ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 [1] Symbol reserved RHSC Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset ...

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NXP Semiconductors • A bit is set in the HcInterruptStatus register. • The corresponding bit in the HcInterruptEnable register is set. • The MIE (Master Interrupt Enable) bit is set. Writing logic bit in this register sets ...

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NXP Semiconductors Table 52. HcInterruptEnable - Host Controller Interrupt Enable register bit description Address: Content of the base address register + 10h Bit Symbol Description 6 RHSC Root Hub Status Change: 0 — Ignore 1 — Enables interrupt generation because ...

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NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 [1] Symbol reserved RHSC Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 54. HcInterruptDisable - Host Controller Interrupt ...

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NXP Semiconductors 11.1.7 HcHCCA register The HcHCCA register contains the physical address of Host Controller Communication Area (HCCA). The bit allocation is given in restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is ...

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NXP Semiconductors Table 57. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation Address: Content of the base address register + 1Ch Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset 0 Access R Bit 15 ...

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NXP Semiconductors Bit 7 Symbol Reset 0 Access R Table 60. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description Address: Content of the base address register + 20h Bit Symbol Description CHED[27:0] Control Head ...

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NXP Semiconductors 11.1.11 HcBulkHeadED register This register (see Table 63. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation Address: Content of the base address register + 28h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 66. ...

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NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 68. HcDoneHead - Host Controller Done Head register bit description Address: Content of the base address register ...

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NXP Semiconductors Table 70. HcFmInterval - Host Controller Frame Interval register bit description Address: Content of the base address register + 34h Bit Symbol Description 31 FIT Frame Interval Toggle: The HCD toggles this bit whenever it loads a new ...

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NXP Semiconductors Table 72. HcFmRemaining - Host Controller Frame Remaining register bit description Address: Content of the base address register + 38h Bit Symbol Description 31 FRT Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) ...

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NXP Semiconductors 11.1.17 HcPeriodicStart register This register has a 14-bit programmable value that determines when is the earliest time for the host controller to start processing the periodic list. For bit allocation, see Table 75. HcPeriodicStart - Host Controller Periodic ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 78. ...

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NXP Semiconductors Bit 7 Symbol Reset 0 Access R [1] The reserved bits should always be written with the reset value. Table 80. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description Address: Content of the base address ...

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NXP Semiconductors Table 81. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation Address: Content of the base address register + 4Ch Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol DRWE Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table ...

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NXP Semiconductors 11.1.22 HcRhPortStatus[4:1] register The HcRhPortStatus[4:1] register is used to control and report port events on a per-port basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word reflects the port status. The ...

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NXP Semiconductors Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description Address: Content of the base address register + 54h Bit Symbol Description 18 PSSC Port Suspend Status Change: This bit is set when the resume ...

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NXP Semiconductors Table 86. HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description Address: Content of the base address register + 54h Bit Symbol Description 4 PRS On read Port Reset Status: When this bit is set by ...

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NXP Semiconductors 11.2 EHCI controller capability registers Other than the OHCI host controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before operational registers. 11.2.1 CAPLENGTH/HCIVERSION register The ...

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NXP Semiconductors Table 89. HCSPARAMS - Host Controller Structural Parameters register bit allocation Address: Content of the base address register + 04h Bit 31 Symbol Reset 0 Access R Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset ...

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NXP Semiconductors Table 90. HCSPARAMS - Host Controller Structural Parameters register bit description Address: Content of the base address register + 04h Bit Symbol Description reserved - 4 PPC Port Power Control: This field indicates whether the ...

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NXP Semiconductors Table 92. HCCPARAMS - Host Controller Capability Parameters register bit description Address: Content of the base address register + 08h Bit Symbol Description reserved - 1 PFLF Programmable Frame List Flag: Default = implementation-dependent. If ...

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NXP Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LHCR IAAD Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 94. USBCMD - USB Command register bit ...

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NXP Semiconductors Table 94. USBCMD - USB Command register bit description Address: Content of the base address register + 20h Bit Symbol Description 5 ASE Asynchronous Schedule Enable: Default = 0. This bit controls whether the host controller skips processing ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ASS PSSTAT Reset 0 Access R Bit 7 [1] Symbol reserved Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset ...

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NXP Semiconductors Table 96. USBSTS - USB Status register bit description Address: Content of the base address register + 24h Bit Symbol Description 3 FLR Frame List Rollover: The host controller sets this bit to logic 1 when the frame ...

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NXP Semiconductors Bit 7 [1] Symbol reserved Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 98. USBINTR - USB Interrupt Enable register bit description Address: Content of the base address ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...

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NXP Semiconductors Table 102. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation Address: Content of the base address register + 34h Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit ...

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NXP Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LPL[2:0] Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table ...

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NXP Semiconductors Table 107. CONFIGFLAG - Configure Flag register bit description Address: Content of the base address register + 60h Bit Symbol Description reserved - 0 CF Configure Flag: The host software sets this bit as the ...

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NXP Semiconductors Table 109. PORTSC Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 Bit Symbol Description reserved - 22 WKOC_E Wake on ...

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NXP Semiconductors Table 109. PORTSC Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 Bit Symbol Description 8 PR Port Reset: Logic 1 means the port ...

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NXP Semiconductors Table 109. PORTSC Port Status and Control 1, 2 register bit description Address: Content of the base address register + 64h + (4 Bit Symbol Description 3 PEDC Port Enable/Disable Change: Logic 1 means the ...

Page 75

NXP Semiconductors 12. Current consumption Table 110 Table 110. Current consumption Cumulative current Total current on pins V CC(I/O)_AUX V plus V plus I(VAUX3V3) DDA_AUX V plus V CC(I/O) I(VREG3V3) Auxiliary current on pins V CC(I/O)_AUX plus V plus V ...

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NXP Semiconductors 13. Limiting values Table 112. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V input/output supply voltage CC(I/O) V 3.3 V regulator input voltage I(VREG3V3) V auxiliary input/output supply voltage CC(I/O)_AUX V ...

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NXP Semiconductors 15. Static characteristics Table 114. Static characteristics 3 3 +85 C; unless otherwise specified. CC(I/O) amb Typical values are 3 CC(I/O) Symbol ...

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NXP Semiconductors Table 117. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2 3 3 +85 C; unless otherwise specified. DDA_AUX amb Symbol Parameter V high-speed ...

Page 79

NXP Semiconductors 16. Dynamic characteristics Table 118. Dynamic characteristics: system clock timing +85 C; unless otherwise specified. CC(I/O) amb Typical values are 3 ...

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NXP Semiconductors Table 121. Dynamic characteristics: high-speed source electrical characteristics +85 C; unless otherwise specified. DDA_AUX amb Typical values are 3 DDA_AUX Symbol ...

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NXP Semiconductors 16.1 Timing Table 124. PCI clock and IO timing +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter PCI clock timing; see Figure 7 T PCICLK ...

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NXP Semiconductors CLK INPUT DELAY Fig 8. CLK OUTPUT DELAY OUTPUT Fig 9. PCI output timing t USBbit 3.3 V crossover point differential data lines the bit duration (USB data). USBbit t is the source jitter ...

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NXP Semiconductors 17. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original ...

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NXP Semiconductors 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction ...

Page 85

NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

Page 86

NXP Semiconductors Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 127. Abbreviations Acronym DID DWORD ED EHCI EMI EOF ...

Page 87

NXP Semiconductors Table 127. Abbreviations Acronym PME POR POST QH SMI SOF STB TD USB VID 20. References [1] Universal Serial Bus Specification — Rev. 2.0 [2] Open Host Controller Interface Specification for USB — Rev. 1.0a [3] Enhanced Host ...

Page 88

NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 89

NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...

Page 90

NXP Semiconductors Interrupt Enable register bit description . . . . . .39 Table 53. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation . . . . . .40 Table 54. HcInterruptDisable - Host Controller Interrupt Disable register bit ...

Page 91

NXP Semiconductors Table 100.FRINDEX - Frame Index register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table 101.N ...

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NXP Semiconductors 25. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration ...

Page 93

NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

Page 94

NXP Semiconductors 11.3.2 USBSTS register . . . . . . . . . . . . . . . . . . . . . . 63 11.3.3 USBINTR register . . . . . . . . . ...

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