ISP1562BE STEricsson, ISP1562BE Datasheet - Page 89

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. REVID - Revision ID register (address 08h)
Table 11. CC - Class Code register (address 09h) bit
Table 12. CC - Class Code register (address 09h) bit
Table 13. CLS - CacheLine Size register (address 0Ch)
Table 14. LT - Latency Timer register (address 0Dh) bit
Table 15. HT - Header Type register (address 0Eh) bit
Table 16. HT - Header Type register (address 0Eh) bit
Table 17. BAR0 - Base Address register 0 (address 10h)
Table 18. SVID - Subsystem Vendor ID register
Table 19. SID - Subsystem ID register (address 2Eh)
Table 20. CP - Capabilities Pointer register (address 34h)
Table 21. IL - Interrupt Line register (address 3Ch) bit
Table 22. IP - Interrupt Pin register (address 3Dh) bit
Table 23. MIN_GNT - Minimum Grant register (address
Table 24. MAX_LAT - Maximum Latency register
Table 25. EHCI-specific PCI registers . . . . . . . . . . . . . . .23
Table 26. SBRN - Serial Bus Release Number register
ISP1562_3
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of OHCI1,
OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .14
VID - Vendor ID register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DID - Device ID register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CMD - Command register (address 04h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CMD - Command register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
STATUS - Status register (address 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
STATUS - Status register (address 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
bit description . . . . . . . . . . . . . . . . . . . . . . . . .18
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
bit description . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
(address 2Ch) bit description . . . . . . . . . . . . . .20
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3Eh) bit description . . . . . . . . . . . . . . . . . . . . .22
(address 3Fh) bit description . . . . . . . . . . . . . .22
Rev. 03 — 14 November 2008
Table 27. FLADJ - Frame Length Adjustment register
Table 28. FLADJ - Frame Length Adjustment register
Table 29. FLADJ value as a function of SOF cycle
Table 30. PORTWAKECAP - Port Wake Capability
Table 31. Power management registers . . . . . . . . . . . . . 24
Table 32. CAP_ID - Capability Identifier register bit
Table 33. NEXT_ITEM_PTR - Next Item Pointer register
Table 34. PMC - Power Management Capabilities
Table 35. PMC - Power Management Capabilities
Table 36. PMCSR - Power Management
Table 37. PMCSR - Power Management
Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 40. PCI bus power and clock control . . . . . . . . . . . 28
Table 41. DATA - Data register bit description . . . . . . . . . 29
Table 42. USB host controller registers . . . . . . . . . . . . . 32
Table 43. HcRevision - Host Controller Revision register
Table 44. HcRevision - Host Controller Revision register
Table 45. HcControl - Host Controller Control register
Table 46. HcControl - Host Controller Control register
Table 47. HcCommandStatus - Host Controller
Table 48. HcCommandStatus - Host Controller
Table 49. HcInterruptStatus - Host Controller
Table 50. HcInterruptStatus - Host Controller
Table 51. HcInterruptEnable - Host Controller
Table 52. HcInterruptEnable - Host Controller
(address 60h) bit description . . . . . . . . . . . . . . 23
(address 61h) bit allocation . . . . . . . . . . . . . . . 23
(address 61h) bit description . . . . . . . . . . . . . . 23
time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
register (address 62h) bit description . . . . . . . 24
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 25
register bit allocation . . . . . . . . . . . . . . . . . . . . 25
register bit description . . . . . . . . . . . . . . . . . . . 26
Control/Status register bit allocation . . . . . . . . 27
Control/Status register bit description . . . . . . . 27
Support Extensions register bit allocation . . . . 28
Support Extensions register bit description . . . 28
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 33
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 34
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 34
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 35
Command Status register bit allocation . . . . . 36
Command Status register bit description . . . . 37
Interrupt Status register bit allocation . . . . . . . 37
Interrupt Status register bit description . . . . . . 38
Interrupt Enable register bit allocation . . . . . . . 39
HS USB PCI host controller
© NXP B.V. 2008. All rights reserved.
ISP1562
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