ISP1562BE STEricsson, ISP1562BE Datasheet - Page 26

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 32.
Address: Value read from address 34h + 0h
Legend: * reset value
Table 33.
Address: Value read from address 34h + 1h
Legend: * reset value
Table 34.
Address: Value read from address 34h + 2h
[1]
ISP1562_3
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.
Symbol
NEXT_ITEM_
PTR[7:0]
Symbol
CAP_ID[7:0]
CAP_ID - Capability Identifier register bit description
NEXT_ITEM_PTR - Next Item Pointer register bit description
PMC - Power Management Capabilities register bit allocation
8.2.3.2 NEXT_ITEM_PTR register
8.2.3.3 PMC register
15
R
R
1
7
1
AUX_C[1:0]
The Next Item Pointer (NEXT_ITEM_PTR) register describes the location of the next item
in the function’s capability list. The value given is an offset into the function’s PCI
configuration space. If the function does not implement any other capabilities defined by
the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in
the list, then this register must be set to 00h. See
The Power Management Capabilities (PMC) register is a 2-byte register, and the bit
allocation is given in
function related to power management.
Access
R
Access
R
14
R
R
1
6
0
Value
01h*
Value
00h*
PME_S[4:0]
Description
ID: This field when 01h identifies the linked list item as being PCI Power
Management registers.
DSI
X
13
R
R
5
0
[1]
Table
Rev. 03 — 14 November 2008
Description
Next Item Pointer: This field provides an offset into the function’s PCI
configuration space, pointing to the location of the next item in the
function’s capability list. If there are no additional items in the capabilities
list, this register is set to 00h.
34. This register provides information on the capabilities of the
reserved
12
R
R
1
4
0
PMI
X
11
R
R
3
0
[1]
Table
D2_S
33.
X
10
R
R
2
0
[1]
HS USB PCI host controller
VER[2:0]
D1_S
R
9
1
R
1
1
© NXP B.V. 2008. All rights reserved.
ISP1562
AUX_C
R
8
0
R
0
0
25 of 93