ISP1562BE STEricsson, ISP1562BE Datasheet - Page 56

• Manufacturer Part Number: ISP1562BE
• Manufacturer: STEricsson

Specifications of ISP1562BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 85.
Address: Content of the base address register + 54h
[1]
Table 86.
Address: Content of the base address register + 54h
ISP1562_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 21
20
19
The reserved bits should always be written with the reset value.
Symbol
reserved
PRSC
OCIC
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description
11.1.22 HcRhPortStatus[4:1] register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
-
Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can
write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — Port reset is not complete.
1 — Port reset is complete.
Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on a
per-port basis. This bit is set when the root hub changes the POCI (Port Overcurrent Indicator) bit.
The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in POCI.
1 — POCI has changed.
The HcRhPortStatus[4:1] register is used to control and report port events on a per-port
basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reflects the port status. The upper word
reflects status change bits. Some status bits are implemented with special write behavior.
If a transaction, token through handshake, is in progress when a write to change port
status occurs, the resulting port status change is postponed until the transaction
completes. Always write logic 0 to the reserved bits. The bit allocation of the register is
given in
reserved
reserved
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Table
[1]
[1]
85.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 03 — 14 November 2008
reserved
[1]
PRSC
PRS
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
[1]
OCIC
POCI
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PSSC
PSS
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI host controller
PESC
LSDA
R/W
R/W
R/W
PES
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2008. All rights reserved.
ISP1562
CSC
CCS
PPS
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
55 of 93