ISP1504CBSTM STEricsson, ISP1504CBSTM Datasheet - Page 51

• Manufacturer Part Number: ISP1504CBSTM
• Manufacturer: STEricsson

Specifications of ISP1504CBSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 28.
ISP1504A_ISP1504C_3
Product data sheet
Bit
7
6
5
4
3
2
1
0
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_SUSPENDM
-
3PIN_FSLS_SERIAL
6PIN_FSLS_SERIAL
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description
10.1.4 OTG Control register
This register controls various OTG functions of the ISP1504. The bit allocation of the OTG
Control register is given in
Description
Interface Protect Disable: Controls circuitry built into the ISP1504 to protect the ULPI
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1504
will automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1504 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1504 attaches weak pull-down
resistors on DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[7:0],
and a weak pull-up resistor on STP.
Indicator Pass-through: Controls whether the complement output is qualified with the
internal A_VBUS_VLD comparator before being used in the V
details, see
0b — The complement output signal is qualified with the internal A_VBUS_VLD comparator
(default).
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see
0b — The ISP1504 will not invert the FAULT signal (default).
1b — The ISP1504 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in
6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to
logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode (default).
1b — Clock will be powered in 3-pin and 6-pin serial mode.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial
interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface (default).
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
Section
Rev. 03 — 7 April 2008
9.5.2.2.
Table
29.
Section
ISP1504A; ISP1504C
9.5.2.2.
ULPI HS USB OTG transceiver
BUS
state in RXCMD. For
© NXP B.V. 2008. All rights reserved.
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