ISP1507B1HNTM STEricsson, ISP1507B1HNTM Datasheet - Page 17

• Manufacturer Part Number: ISP1507B1HNTM
• Manufacturer: STEricsson

Specifications of ISP1507B1HNTM

• Lead Free Status / RoHS Status: Compliant

Table 5.
[1]
Table 6.
[1]
CD00269905
Product data sheet
Signal
Reserved
INT
Reserved
Signal
TX_ENABLE
TX_DAT
TX_SE0
INT
RX_DP
RX_DM
RX_RCV
Reserved
O = output.
I = input; O = output.
Signal mapping during low-power mode
Signal mapping for 6-pin serial mode
9.1.3 6-pin full-speed or low-speed serial mode
9.1.4 3-pin full-speed or low-speed serial mode
Maps to
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
Maps to
DATA2
DATA3
DATA[7:4]
If the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507x1 to 6-pin serial mode. In 6-pin serial mode, the
DATA[7:0] bus definition changes to that shown in
link sets the 6PIN_FSLS_SERIAL bit in the INTF_CTRL register (see
logic 1. To exit 6-pin serial mode, the link asserts STP. This is provided primarily for links
that contain legacy full-speed or low-speed functionality, providing a more cost-effective
upgrade path to high-speed. An interrupt pin is also provided to inform the link of USB
events. If the link requires CLOCK to be running during 6-pin serial mode, the
CLOCK_SUSPENDM register bit must be set to logic 1.
For more information on 6-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
If the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed
USB data, it can set the ISP1507x1 to 3-pin serial mode. In 3-pin serial mode, the data
bus definition changes to that shown in
the 3PIN_FSLS_SERIAL bit in the INTF_CTRL register (see
exit 3-pin serial mode, the link asserts STP. This is primarily provided for links that contain
legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path
to high-speed. An interrupt pin is also provided to inform the link of USB events. If the link
requires CLOCK to be running during 3-pin serial mode, the CLOCK_SUSPENDM
register bit must be set to logic 1.
For more information on 3-pin serial mode enter and exit protocols, refer to UTMI+ Low
Pin Interface (ULPI) Specification Rev. 1.1.
Direction
O
O
O
Direction
I
I
I
O
O
O
O
O
[1]
[1]
Description
active-HIGH transmit enable
transmit differential data on DP and DM
transmit single-ended zero on DP and DM
active-HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
single-ended receive data from DP
single-ended receive data from DM
differential receive data from DP and DM
reserved; the ISP1507x1 will drive this pin to LOW
Description
reserved; the ISP1507x1 will drive this pin to LOW
active-HIGH interrupt indication; will be asserted whenever any unmasked
interrupt occurs
reserved; the ISP1507x1 will drive these pins to LOW
Rev. 03 — 26 July 2010
…continued
Table
ISP1507A1; ISP1507B1
7. To enter 3-pin serial mode, the link sets
Table
6. To enter 6-pin serial mode, the
ULPI HS USB OTG transceiver
Section
© ST-ERICSSON 2010. All rights reserved.
11.1.3) to logic 1. To
Section
11.1.3) to
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