ISP1506ABS STEricsson, ISP1506ABS Datasheet - Page 31

• Manufacturer Part Number: ISP1506ABS
• Manufacturer: STEricsson

Specifications of ISP1506ABS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
ISP1506A_ISP1506B_2
Product data sheet
For more information, refer to
Rev.
b. Host chirp: If the host does not detect the peripheral chirp, it must continue
c. High-speed idle: The peripheral must detect a minimum of Chirp K-J-K-J-K-J. Each
1.1”.
than 7 ms after reset time T
up its clock within 5.6 ms, leaving 200 s for the link to start transmitting the
Chirp K, and 1.2 ms for the Chirp K to complete (worst case with 10 % slow clock).
asserting SE0 until the end of reset. If the host detects the peripheral Chirp K for
no less than 2.5 s, then no more than 100 s after the bus leaves the Chirp K
state, the host sends a TXCMD (NOPID) with an alternating sequence of Chirp Ks
and Chirp Js. Each Chirp K or Chirp J must last no less than 40 s and no longer
than 60 s.
Chirp K and Chirp J must be detected for at least 2.5 s. After seeing that
minimum sequence, the peripheral sets TERMSELECT = 0b and
OPMODE[1:0] = 00b. The peripheral is now in high-speed mode and sees !squelch
(01b on LINESTATE). When the peripheral sees squelch (10b on LINESTATE), it
knows that the host has completed chirp and waits for Hi-Speed USB traffic to
begin. After transmitting the chirp sequence, the host changes OPMODE[1:0] to
00b and begins sending USB packets.
Rev. 02 — 28 August 2008
Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification
0
. If the peripheral is in low-power mode, it must wake
ISP1506A; ISP1506B
ULPI HS USB OTG transceiver
© NXP B.V. 2008. All rights reserved.
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