ISP1705AETTM STEricsson, ISP1705AETTM Datasheet - Page 61

• Manufacturer Part Number: ISP1705AETTM
• Manufacturer: STEricsson

Specifications of ISP1705AETTM

• Lead Free Status / RoHS Status: Compliant

Table 42.
Table 44.
ISP1705_2
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
USB_INTR_L - USB interrupt latch register (address R = 14h) bit allocation
DEBUG - Debug register (address R = 15h) bit allocation
11.12 DEBUG register
R
R
7
0
7
0
Table 43.
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
Table 45.
Bit
7 to 5 reserved
4
3
2
1
0
Bit
7 to 2
1
0
reserved
Symbol
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
R
R
6
0
6
0
USB_INTR_L - USB interrupt latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit description
Symbol
-
LINESTATE1
LINESTATE0
R
R
5
0
5
0
Rev. 02 — 21 January 2009
reserved
Description
-
ID ground latch: Automatically set when an unmasked event occurs
on ID_GND. Cleared when this register is read.
Session end latch: Automatically set when an unmasked event
occurs on SESS_END. Cleared when this register is read.
Session valid latch: Automatically set when an unmasked event
occurs on SESS_VLD. Cleared when this register is read.
V
on A_VBUS_VLD. Cleared when this register is read.
Host disconnect latch: Automatically set when an unmasked event
occurs on HOST_DISCON. Cleared when this register is read.
BUS
ID_GND_L
valid latch: Automatically set when an unmasked event occurs
Description
reserved
Line state 1: Contains the current value of LINESTATE 1
Line state 0: Contains the current value of LINESTATE 0
R
R
4
0
4
0
SESS_
END_L
R
R
3
0
3
0
Table
VALID_L
SESS_
ULPI Hi-Speed USB transceiver
R
R
2
0
44. This register indicates the
2
0
VALID_L
STATE1
© ST-NXP Wireless 2009. All rights reserved.
VBUS_
LINE
R
R
1
0
1
0
ISP1705
DISCON_L
STATE0
HOST_
LINE
R
R
0
0
0
0
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