CY7C68000-48BAC Cypress Semiconductor Corp, CY7C68000-48BAC Datasheet
CY7C68000-48BAC
Specifications of CY7C68000-48BAC
Related parts for CY7C68000-48BAC
CY7C68000-48BAC Summary of contents
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... CY7C68000 TX2™ USB 2.0 UTMI Transceiver Cypress Semiconductor Corporation Document #: 38-08016 Rev. *C • 3901 North First Street • CY7C68000 , San Jose CA 95134 • 408-943-2600 Revised February 20, 2003 ...
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... PACKAGE DIAGRAMS ............................................................................................................... 12 Figure 1-1. Block Diagram ....................................................................................................................... 3 Figure 5-1. CY7C68000 48-pin FBGA Pin Assignment ........................................................................... 5 Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment ........................................................................... 6 Figure 9-1. 60-MHz Interface Timing Constraints .................................................................................. 11 Figure 9-2. 30-MHz Timing Interface Timing Constraints ...................................................................... 11 Figure 11-1. 56-lead Shrunk Small Outline Package O56 ..................................................................... 12 Figure 11-2 ...
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... Supports USB 2.0 test modes. Document #: 38-08016 Rev. *C CY7C68000 CY7C68000 PLL_480 Fast Traffic Elasticity Digital Sync Buffer Fast Digital Figure 1-1. Block Diagram CY7C68000 UTMI CLK Digital Digital Tx UTMI CLK UTMI Rx Ctl UTMI Rx Data 8/16 BIDI Option Also UTMI Rx Data 8/16 ...
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... The operational modes are controlled by the OpMode signals. The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input. Document #: 38-08016 Rev. *C has reached 3.3V. CC CY7C68000 Page ...
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... DPLUS/DMINUS Impedance Termination The CY7C68000 does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part. ...
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... Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment 5.1 CY7C68000 Pin Descriptions [1] Table 5-1. Pin Descriptions 56 48 Name Type 11 B6 AVCC Power 15 C6 AVCC Power 14 A1 AGND Power 18 B1 AGND Power 16 A3 DPLUS I/O DMINUS I/O/Z Note: 1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby ...
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... HS termination 1: FS termination N/A Suspend. Places the CY7C68000 in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume opera- tions. While suspended, TermSelect must always mode to ensure that the 1.5 K ohm pull-up on DPLUS remains powered. ...
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... TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000 will load the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE should immediately present the data for the next transfer on the data bus Receive Data Valid ...
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... Connect to 3.3V power source Connect to 3.3V power source. CC N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. CY7C68000 Description Page ...
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... Document #: 38-08016 Rev. *C Conditions 0< V < OUT I = –4 mA OUT Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins Includes 1.5k-ohm internal pull-up Without 1.5k-ohm internal pull-up Normal operation OPMOD[1: Normal operation OPMOD[1: CY7C68000 + 0.5V CC Parallel Resonant Min. Typ. Max. Unit 3.0 3.3 3 5.25 V –0.5 0.8 V ± ...
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... Minimum set-up time for Data (Transmit direction) DSU_MIN T Minimum hold time for Data (Transmit direction) DH_MIN Document #: 38-08016 Rev. *C TCH_MIN TCSU_MIN TDH_MIN Figure 9-1. 60-MHz Interface Timing Constraints Description TCH_MIN TCSU_MIN TDH_MIN TVH_MIN TVSU_MIN Description CY7C68000 TCCO TDCO Min. Typ. Max. Unit ...
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... VH_MIN T Clock to ValidH out time (Receive direction) CVO 10.0 Ordering Information Table 10-1. Ordering Information Ordering Code CY7C68000-48BAC CY7C68000-56PVC CY7C68000-56PVCT 11.0 Package Diagrams The TX2 is available in two packages: • 56-pin SSOP • 48-pin FBGA. Figure 11-1. 56-lead Shrunk Small Outline Package O56 Document #: 38-08016 Rev ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C68000 51-85096-*E ...
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... Document History Page Document Title: CY7C68000 TX2™ USB 2.0 UTMI Transceiver Document Number: 38-08016 Issue REV. ECN NO. Date ** 112019 03/01/02 *A 113885 07/01/02 *B 118521 11/18/02 *C 124507 02/21/03 Document #: 38-08016 Rev. *C Orig. of Change KKU New data sheet KKU Updated pinouts on BGA package, signal names. ...