SAA7118E/V1/M5,557 Trident Microsystems, Inc., SAA7118E/V1/M5,557 Datasheet - Page 126

• Manufacturer Part Number: SAA7118E/V1/M5,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7118E/V1/M5,557

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 85.
Table 86.
Table 87.
See
Table 88.
Table 89.
SAA7118_7
Product data sheet
Recommended value
Vertical offset
Minimum value 0
Maximum value 312
Value for 50 Hz 625 lines input
Value for 60 Hz 525 lines input
Bit
D7
D6
Bit
D7
D[5:0]
Bit
D[5:0]
Horizontal offset
Section 10.6.4
Horizontal offset for slicer; slicer set 59h and 5Bh
Vertical offset for slicer; slicer set 5Ah and 5Bh
Field offset, and MSBs for horizontal and vertical offsets; slicer set 5Bh[7:6]
Header and data identification (DID; ITU 656) code control; slicer set 5Dh[7:0]
Sliced data identification (SDID) code; slicer set 5Eh[5:0]
Description
field offset
recode
Description
field ID and V-blank selection
for text output (F and V
reference selection)
default; DID[5:0] = 00h
special cases of DID
programming
Description
SDID codes
10.6.4 Subaddress 59h
10.6.5 Subaddress 5Ah
10.6.6 Subaddress 5Bh
10.6.7 Subaddress 5Dh
10.6.8 Subaddress 5Eh
and
Section 10.6.5
for HOFF[10:8] 5Bh[2:0] and VOFF8[5Bh[4]].
Control bits 5Bh[2:0]
HOFF[10:8] = 3h
Control bit 5Bh[4]
VOFF8
0
1
0
0
Symbol
FOFF
RECODE
Symbol
FVREF
DID[5:0]
DID[5:0]
Symbol
SDID[5:0]
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
Value
0
1
0
1
Value
0
1
00 0000
11 1110
11 1111
Value
00h
Function
no modification of internal field indicator (default
for 50 Hz 625 lines input sources)
invert field indicator (default for 60 Hz 525 lines
input sources)
leave data unchanged (default)
convert 00h and FFh data bytes into 03h and FCh
Function
F and V output of slicer is LCR table dependent
F and V output is taken from decoder real-time
signals EVEN_ITU and VBLNK_ITU
ANC header framing; see
DID[5:0] = 3Eh SAV/EAV framing, with FVREF = 1
DID[5:0] = 3Fh SAV/EAV framing, with FVREF = 0
Function
default
Control bits 59h[7:0]
HOFF[7:0] = 47h
Control bits 5Ah[7:0]
VOFF[7:0]
00h
38h
03h
06h
Figure 41
SAA7118
© NXP B.V. 2008. All rights reserved.
and
126 of 177
Table 21