SAA7118E/V1/M5,557 Trident Microsystems, Inc., SAA7118E/V1/M5,557 Datasheet - Page 138

SAA7118E/V1/M5,557

Manufacturer Part Number
SAA7118E/V1/M5,557
Description
Manufacturer
Trident Microsystems, Inc.
Datasheet

Specifications of SAA7118E/V1/M5,557

Adc/dac Resolution
9b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAA7118E/V1/M5,557
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
NXP Semiconductors
Table 122. Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]]
[1]
Table 123. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]]
Table 124. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]]
Table 125. Prescaler DC gain and FIR prefilter control; register set A [A2h[7:4]] and B [D2h[7:4]]
[1]
SAA7118_7
Product data sheet
Vertical output acquisition window
definition number of desired output
lines in Y (vertical) direction
No output
1 pixel
Maximum possible number of output
lines = 4095
Horizontal integer prescaling ratio (XPSC)
Not allowed
Downscale = 1
Downscale =
...
Downscale =
Horizontal prescaler accumulation sequence length (XACL)
Accumulation length = 1
Accumulation length = 2
...
Accumulation length = 64
FIR prefilter control
Luminance FIR filter bypassed
H_y(z) =
H_y(z) =
H_y(z) =
Chrominance FIR filter bypassed
H_uv(z) =
H_uv(z) =
H_uv(z) =
If the desired output length is greater than the number of scaled output lines, the processing is cut.
X = don’t care.
1
1
1
4
8
8
1
1
1
4
32
8
(1 2 1)
( 1 1 1.75 4.5 1.75 1 1)
(1 2 2 2 1)
[1]
(1 2 1)
(1 2 2 2 1)
1
1
(3 8 10 8 3)
10.7.9 Subaddresses A0h to A2h
2
63
Control bits
A [9Fh[3:0]] and
B [CFh[3:0]]
YD11 YD10 YD9
0
0
1
0
0
1
Rev. 07 — 7 July 2008
0
0
1
Multistandard video decoder with adaptive comb filter
YD8
0
0
1
Control bits D5 to D0
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0
0
0
0
...
1
Control bits D5 to D0
XACL5 XACL4 XACL3 XACL2 XACL1 XACL0
0
0
...
1
Control bits D7 to D4
PFUV1
X
X
X
X
0
0
1
1
A [9Eh[7:0]] and B [CEh[7:0]]
YD7
0
0
1
YD6
0
0
1
0
0
0
...
1
0
0
...
1
PFUV0
X
X
X
X
0
1
0
1
YD5
0
0
1
0
0
0
...
1
0
0
...
1
YD4
0
0
1
0
0
0
...
1
0
0
...
1
PFY1
0
0
1
1
X
X
X
X
YD3
0
0
1
SAA7118
[1]
© NXP B.V. 2008. All rights reserved.
YD2
0
0
1
0
0
1
...
1
0
0
...
1
PFY0
0
1
0
1
X
X
X
X
YD1
0
0
1
138 of 177
0
1
0
...
1
0
1
...
1
YD0
0
1
1

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