SAA7118E/V1/M5,557 Trident Microsystems, Inc., SAA7118E/V1/M5,557 Datasheet - Page 45

• Manufacturer Part Number: SAA7118E/V1/M5,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAA7118E/V1/M5,557

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
SAA7118_7
Product data sheet
The flow is controlled by internal data valid and data request flags (internal handshake
signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer.
Depending on the actual programmed scaling parameters the effective buffer can exceed
to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced
significantly.
The high performance video scaler in the SAA7118 has the following major blocks:
The overall H and V zooming (HV_zoom) is restricted by the input/output data rate
relationships. With a safety margin of 2 % for running in and running out, the maximum
HV_zoom is equal to:
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate,
2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate
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•
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•
•
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•
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Acquisition control (horizontal and vertical timer) and task handling (the
region/field/frame based processing)
Prescaler, for horizontal downscaling by an integer factor, combined with appropriate
band limiting filters, especially anti-aliasing for CIF format
Brightness, saturation, contrast control for scaled output data
Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for
videophone application, converting 240 into 288 lines, Y-C
Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and
downscale, or phase accurate ACcumulation Mode (ACM) for large downscaling
ratios and better alias suppression
Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for
arbitrary non-integer scaling ratios, supporting conversion between square and
rectangular pixel sampling
Output formatter for scaled Y-C
used for raw data)
FIFO, 32-bit wide, with 64 pixel capacity in Y-C
Output interface, 8-bit or 16-bit (only if extended by H port) data pins wide,
synchronous or asynchronous operation, with stream events on discrete pins, or
coded in the data stream
1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to:
(ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
0.98
16.666 ms 22 64 s
-------------------------------------------------------- -
720 240 1 37 ns
–
0.98
Rev. 07 — 7 July 2008
0.98
---------------------------------------------------------------------------------------------------------------------------- -
in_pixel in_lines out_cycle_per_pix T_out_clk
Multistandard video decoder with adaptive comb filter
---------------------------------------------------- -
720 288 2 37 ns
=
20 ms 24 64 s
B
2.34
-C
R
T_input_field - T_v_blanking
–
4 : 2 : 2, Y-C
B
-C
B
-C
R
=
formats
R
1.18
4 : 1 : 1 and Y only (format also
B
-C
R
4 : 2 : 2)
SAA7118
© NXP B.V. 2008. All rights reserved.
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