SAA7118E/V1/M5.557 NXP Semiconductors, SAA7118E/V1/M5.557 Datasheet - Page 140

• Manufacturer Part Number: SAA7118E/V1/M5.557
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E/V1/M5.557

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 130. Horizontal luminance scaling increment; register set A [A8h[7:0]; A9h[7:0]] and B [D8h[7:0]; D9h[7:0]]
[1]
Table 131. Horizontal luminance phase offset; register set A [AAh[7:0]] and B [DAh[7:0]]
Table 132. Horizontal chrominance scaling increment; register set A [ACh[7:0]; ADh[7:0]] and B [DCh[7:0];
[1]
Table 133. Horizontal chrominance phase offset; register set A [AEh[7:0]] and B [DEh[7:0]]
SAA7118_7
Product data sheet
Horizontal luminance
scaling increment
Scale =
zoom
Scale =
defined by data path
structure
Scale =
Scale = 1, equals 1024
Scale =
Scale =
Horizontal luminance
phase offset
Offset = 0
Offset =
Offset =
Offset =
Horizontal chrominance
scaling increment
This value must be set to
the luminance value
1
Horizontal chrominance
phase offset
This value must be set to
1
2
2
XSCY[15:0]
XPHY[7:0]
Bits XSCY[15:13] are reserved and are set to logic 0.
Bits XSCC[15:13] are reserved and are set to logic 0.
1024
1024
1024
1024
1024
1
32
255
32
32
DDh[7:0]]
32
1
294
1023
1025
8191
pixel
10.7.11 Subaddresses A8h to AEh
= 1 pixel
(theoretical)
pixel
, lower limit
zoom
downscale 0000
downscale 0001
Control bits
A [A9h[7:4]]
B [D9h[7:4]]
XSCY[15:12]
0000
0000
0000
0000
Control bits D7 to D0
XPHY7
0
0
0
1
Control bits
A [ADh[7:4]]
B [DDh[7:4]]
XSCC[15:12]
0000
0000
0001
Control bits D7 to D0
XPHC7
0
0
1
XPHY6
0
0
0
1
XPHC6
0
0
1
[1]
[1]
Rev. 07 — 7 July 2008
A [A9h[3:0]]
B [D9h[3:0]]
XSCY[11:8]
0000
0001
0011
0100
0100
1111
XPHY5
0
0
1
1
A [ADh[3:0]]
B [DDh[3:0]]
XSCC[11:8]
0000
0000
1111
XPHC5
0
0
1
Multistandard video decoder with adaptive comb filter
XPHY4
0
0
0
1
XPHC4
0
0
1
A [A8h[7:4]]
B [D8h[7:4]]
XSCY[7:4]
0000
0010
1111
0000
0000
1111
XPHY3
0
0
0
1
A [ACh[7:4]]
B [DCh[7:4]]
XSCC[7:4]
0000
0000
1111
XPHC3
0
0
1
0
0
1
0
0
1
XPHY2
0
XPHC2
A [A8h[3:0]]
B [D8h[3:0]]
XSCY[3:0]
0000
0110
1111
0000
0001
1111
XPHY1
0
0
0
1
A [ACh[3:0]]
B [DCh[3:0]]
XSCC[3:0]
0000
0001
1111
XPHC1
0
0
1
SAA7118
© NXP B.V. 2008. All rights reserved.
XPHY0
0
1
0
1
XPHC0
0
1
1
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