SAA7118E/V1/M5.557 NXP Semiconductors, SAA7118E/V1/M5.557 Datasheet - Page 70

• Manufacturer Part Number: SAA7118E/V1/M5.557
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E/V1/M5.557

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
9. Input/output interfaces and ports
SAA7118_7
Product data sheet
9.1 Analog terminals
The SAA7118 has 5 different I/O interfaces:
The SAA7118 has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and
AI11 to AI14 for composite video CVBS or S-video Y/C signal pairs or component video
input signals RGB plus separate sync (or Y-P
Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed
to two ADC channels, one for the video contents, the other for sync conversion.
Additionally, there are four differential reference inputs, which must be connected to
ground via a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are
no peripheral components required other than these decoupling capacitors and
18 /56
example in
Clamp and gain control for the four ADCs are also integrated. An analog video output
(pin AOUT) is provided for testing purposes.
Table 25.
[1]
Symbol
AI11 to AI14
AI21 to AI24
AI31 to AI34
AI41 to AI44
AOUT
AI1D, AI2D,
AI3D and AI4D
•
•
•
•
•
•
Analog video input interface, for analog CVBS and/or Y and C input signals and/or
component video signals
Audio clock port
Digital real-time signal port (RT port)
Digital video expansion port (X port), for unscaled digital video input and output
Digital image port (I port) for scaled video data output and programming
Digital host port (H port) for extension of the image port or expansion port from 8-bit
to 16-bit
Pin numbers for QFP160 in parenthesis.
Analog pin description
termination resistors, one set per connected input signal; see application
Figure
Pin
J2, K1, K2 and L3
(27, 29, 31 and 34)
G4, G3, H2 and J3
(19, 21, 23 and 26)
E3, F2, F3 and G1
(11, 13, 15 and 18)
B1, D2, D1 and E1
(2, 5, 7 and 10)
M1 (36)
K3, H1, F1 and D3
(30, 22, 14 and 6)
92. Four anti-alias filters are integrated.
[1]
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
I/O
I
O
I
Description
analog video signal inputs, e.g.
16 CVBS signals or eight Y/C pairs,
or four RGB plus separate sync (or
Y-P
groups can be connected
simultaneously to this device; many
combinations are possible; see
Figure 50
analog video output, for test
purposes
analog reference pins for differential
ADC operation; connect to ground
via 47 nF
B
B
-P
-P
R
R
plus separate sync) signal
plus separate sync).
to
Figure 90
SAA7118
© NXP B.V. 2008. All rights reserved.
Bit
MODE5 to
MODE0
AOSL2 to
AOSL0
-
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