ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet
ADV7341BSTZ
Specifications of ADV7341BSTZ
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ADV7341BSTZ Summary of contents
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FEATURES 74.25 MHz 20-/30-bit high definition input support Compliant with SMPTE 274 M (1080i), 296 M (720p), and 240 M (1035i) 6 Noise Shaped Video® (NSV) 12-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC ...
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ADV7340/ADV7341 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagram .............................................................. 5 Specifications ..................................................................................... 6 Power Supply and Voltage Specifications .................................. 6 Voltage Reference Specifications ................................................ 6 Input Clock ...
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Copy Generation Management System ........................................ 77 SD CGMS ..................................................................................... 77 ED CGMS..................................................................................... 77 HD CGMS .................................................................................... 77 CGMS CRC Functionality ......................................................... 77 SD Wide Screen Signaling .............................................................. 80 SD Closed Captioning .................................................................... 81 Internal Test Pattern Generation ................................................... 82 SD ...
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ADV7340/ADV7341 GENERAL DESCRIPTION The ADV7340/ADV7341 are high speed, digital-to-analog video encoders in a 64-lead LQFP package. Six high speed, NSV, 3.3 V, 12-bit video DACs provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition ...
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DGND (2) V (2) DD GND_IO VBI DATA SERVICE INSERTION V DD_IO 8-/10-/16-/20-/ RGB 24-/30-BIT 4:2:2 TO 4:4 YCrCb SD MATRIX DEINTERLEAVE VIDEO DATA R RGB ASYNC BYPASS G/B YCbCr 8-/10-/16-/20-/ 24-/30-BIT SDR/DDR ED/HD ED/HD INPUT HDTV 4:2:2 ...
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ADV7340/ADV7341 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 2. Parameter SUPPLY VOLTAGES DD_IO POWER SUPPLY REJECTION RATIO VOLTAGE REFERENCE SPECIFICATIONS ...
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ANALOG OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter Full-Drive Output Current (Full-Scale) ...
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ADV7340/ADV7341 DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 8. Parameter VIDEO DATA ...
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DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 9. Parameter VIDEO DATA AND ...
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ADV7340/ADV7341 MPU PORT TIMING SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 10. Parameter 2 1 ...
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VIDEO PERFORMANCE SPECIFICATIONS Table 12. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 1 Differential Nonlinearity +ve 1 Differential Nonlinearity −ve STANDARD DEFINTION (SD) MODE Luminance ...
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ADV7340/ADV7341 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: • clock high time 9 • clock low time 10 • data setup time 11 • data hold ...
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CLKIN_A S_HSYNC, CONTROL INPUTS S_VSYNC CONTROL OUTPUTS Figure 4. SD Only, 24-/30-Bit, 4:4:4 ...
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ADV7340/ADV7341 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK CONTROL OUTPUTS Figure 7. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) ...
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CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK C2/ Cb0 Cr0 CLKIN_A S_HSYNC, CONTROL INPUTS S_VSYNC S9 TO S2/ ...
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ADV7340/ADV7341 CLKIN_A CONTROL OUTPUTS Figure 13. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111) Y OUTPUT P_HSYNC P_VSYNC P_BLANK ...
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Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR ...
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ADV7340/ADV7341 Y OUTPUT P_HSYNC P_VSYNC P_BLANK AND b AS PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN ...
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S_HSYNC S_VSYNC Y0* *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 18. SD Input Timing Diagram (Timing Mode SDA SCL Figure 19. MPU Port Timing ...
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ADV7340/ADV7341 ABSOLUTE MAXIMUM RATINGS Table 13. 1 Parameter V to AGND DGND PGND GND_IO DD_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD_IO V DGND Table 15. Pin Function Descriptions Input/ Pin No. Mnemonic Output 13 ...
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ADV7340/ADV7341 Input/ Pin No. Mnemonic Output 45, 35 COMP1, O COMP2 44, 43 DAC 1, DAC 2, DAC 3 39, 38, 37 DAC 4, DAC 5, O DAC 6 21 SCL I 20 SDA I/O 19 ALSB I ...
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TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response ED ...
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ADV7340/ADV7341 Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND IN ...
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Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 140 160 FREQUENCY (MHz) Figure 33. SD, 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 ...
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ADV7340/ADV7341 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. SD Luma QCIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 40. SD ...
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FREQUENCY (MHz) Figure 45. SD Chroma CIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – Figure 46. SD Chroma QCIF Low-Pass ...
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ADV7340/ADV7341 MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV7340/ADV7341 through a 2-wire serial (I bus. After power-up or reset, the MPU port is configured for operation. To obtain information about communicating with ...
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SDA SCL S 1–7 8 START ADDR R/W ACK SUBADDRESS ACK WRITE S SLAVE ADDR A(S) SUBADDR SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SUBADDR SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP ...
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ADV7340/ADV7341 REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7340/ADV7341 via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines which register the next ...
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SR7 to SR0 Register Bit Description 0x02 Mode Reserved. Register 0 HD interlace external HSYNC and Test pattern black bar. Manual CSC matrix adjust Sync on RGB RGB/YPrPb output select SD sync output enable ED/HD sync output enable 0x03 ED/HD ...
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ADV7340/ADV7341 Table 19. Register 0x0A to Register 0x10 SR7 to SR0 Register Bit Description 0x0A DAC 4, DAC 5, DAC 6 Positive gain to output levels DAC output voltage Negative gain to DAC output voltage 0x0B DAC 1, DAC 2, ...
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Table 20. Register 0x12 to Register 0x17 SR7 to SR0 Register 0x12 Pixel port readback (S bus MSBs) 0x13 Pixel port readback (Y bus MSBs) 0x14 Pixel port readback (C bus MSBs) 0x15 Pixel port readback (S, Y, and C ...
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ADV7340/ADV7341 Table 21. Register 0x30 SR7 to SR0 Register Bit Description 0x30 ED/HD Mode ED/HD output Register 1 standard ED/HD input synchronization format ED/HD standard 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or ...
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Table 22. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD pixel data valid Register 2 Reserved ED/HD test pattern enable ED/HD test pattern hatch/field ED/HD VBI open ED/HD undershoot limiter ED/HD sharpness filter ...
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ADV7340/ADV7341 Table 23. Register 0x34 to Register 0x35 SR7 to SR0 Register Bit Description 0x34 ED/HD Mode ED/HD timing reset Register 5 ED/HD HSYNC control ED/HD VSYNC control ED/HD blank polarity ED Macrovision® enable Reserved ED/HD VSYNC/field input Horizontal/vertical counters ...
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Table 24. Register 0x36 to Register 0x43 SR7 to SR0 Register Bit Description 0x36 ED/HD Y level 2 ED/HD Test Pattern Y level 2 0x37 ED/HD Cr level ED/HD Test Pattern Cr level 2 0x38 ED/HD Test Pattern Cb level ...
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ADV7340/ADV7341 SR7 to SR0 Register Bit Description 0x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128) 0x55 ED/HD Gamma B7 ED/HD Gamma Curve B (Point 160) 0x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192) 0x57 ED/HD Gamma ...
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SR7 to SR0 Register 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter Threshold B 0x5D ED/HD Adaptive Filter Threshold Logic 0 or Logic 1. Table 27. Register 0x5E to Register 0x6E SR7 to SR0 ...
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ADV7340/ADV7341 Table 28. Register 0x80 to Register 0x83 SR7 to SR0 Register Bit Description 0x80 SD Mode SD standard Register 1 SD luma filter SD chroma filter 0x82 SD Mode SD PrPb SSAF Register 2 SD DAC Output 1 SD ...
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Table 29. Register 0x84 to Register 0x89 SR7 to SR0 Register Bit Description 0x84 SD Mode Reserved Register 4 SD SFL/SCR/TR mode select SD active video length SD chroma SD burst SD color bars SD luma/chroma swap 0x86 SD Mode ...
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ADV7340/ADV7341 SR7 to SR0 Register Bit Description 0x88 SD Mode Reserved. Register 7 SD noninterlaced mode SD double buffering SD input format SD digital noise reduction SD gamma correction enable SD gamma correction curve select 0x89 SD Mode SD undershoot ...
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SR7 to SR0 Register Bit Description 0x8B SD Timing Register 1 SD HSYNC width (applicable in master modes only, that is, Subaddress 0x8A, Bit HSYNC to VSYNC delay SD HSYNC to VSYNC rising edge delay (Mode ...
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ADV7340/ADV7341 Table 31. Register 0x99 to Register 0xA5 SR7 to SR0 Register Bit Description 0x99 SD CGMS/WSS 0 SD CGMS data SD CGMS CRC SD CGMS on odd fields SD CGMS on even fields SD WSS 0x9A SD CGMS/WSS 1 ...
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SR7 to SR0 Register Bit Description 0xA3 SD DNR 0 Coring gain border (in DNR mode, the values in brackets apply) Coring gain data (in DNR mode, the values in brackets apply) 0xA4 SD DNR 1 DNR threshold Border area ...
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ADV7340/ADV7341 Table 32. Register 0xA6 to Register 0xBB SR7 to SR0 Register Bit Description 0xA6 SD Gamma A0 SD Gamma Curve A (Point 24) 0xA7 SD Gamma A1 SD Gamma Curve A (Point 32) 0xA8 SD Gamma A2 SD Gamma ...
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Table 34. Register 0xC9 to Register 0xCE SR7 to SR0 Register Bit Description 0xC9 Teletext control Teletext enable Teletext request mode Teletext input pin select Reserved 0xCA Teletext request Teletext request falling control edge position control Teletext request rising edge ...
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ADV7340/ADV7341 INPUT CONFIGURATION The ADV7340/ADV7341 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7340/ADV7341 default to standard definition only (SD only) on power-up. Table 36 provides an overview of all ...
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Table 36. Input Configuration S 1 Input Mode 000 SD only 8-/10-bit YCrCb 2, 3 YCrCb 16-/20-bit YCrCb 8-/10-bit 2, 3 YCrCb 16-/20-bit YCrCb 24-/30-bit R 4 RGB ...
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ADV7340/ADV7341 ENHANCED DEFINITION/HIGH DEFINITION ONLY Subaddress 0x01, Bits[6:4] = 001 or 010 Enhanced definition (ED) or high definition (HD) YCrCb data can be input in either 4:2:2 or 4:4:4 format. If desired, dual data rate (DDR) pixel data inputs can ...
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Whether the ED/HD Y data is clocked in on the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (see the input sequence shown in Figure 52 and Figure 53). S_VSYNC, 2 S_HSYNC SD 27MHz DECODER CLKIN_A ...
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ADV7340/ADV7341 OUTPUT CONFIGURATION The ADV7340/ADV7341 support a number of different output configurations. Table 37 to Table 40 list all possible output configurations. Table 37. SD Only Output Configurations RGB/YPrPb SD DAC SD DAC Output Select 1 Output 2 Output 1 ...
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DESIGN FEATURES OUTPUT OVERSAMPLING The ADV7340/ADV7341 include two on-chip phase-locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data. Table 41 shows the various oversampling rates supported in the ADV7340/ADV7341. SD Only, ED Only, and HD ...
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ADV7340/ADV7341 HD INTERLACE EXTERNAL P_HSYNC AND P_VSYNC CONSIDERATIONS If the encoder revision code (Subaddress 0xBB, Bits[7:6 higher, the user should set Subaddress 0x02, Bit 1 to high to ensure exactly correct timing in HD interlace modes when ...
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DISPLAY 307 NO F RESET APPLIED SC DISPLAY 307 F RESET APPLIED SC Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 01) COMPOSITE 1 VIDEO H/L TRANSITION COUNT START 128 RTC TIME SLOT 01 1 FOR ...
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ADV7340/ADV7341 In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is ...
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ANALOG VIDEO C INPUT PIXELS Y r NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO LINE HSYNC FIELD PIXEL DATA FILTERS Table 44 shows an overview of the programmable filters available on the ADV7340/ADV7341. Table ...
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ADV7340/ADV7341 EXTENDED (SSAF) PrPb FILTER MODE 0 –10 –20 –30 –40 –50 – FREQUENCY (MHz) Figure 65. PrPb SSAF Filter If this filter is disabled, one of the chroma filters shown in Table 45 can ...
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Table 46. Sample Color Values for EIA 770.2/EIA770.3 ED/HD Output Standard Selection Sample Color Y Value Cr Value White 235 (0xEB) 128 Black 16 (0x10) 128 Red 81 (0x51) 240 Green 145 (0x91) 34 Blue 41 (0x29) 110 Yellow 210 ...
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ADV7340/ADV7341 On power-up, the CSC matrix is programmed with the default values shown in Table 50. Table 50. ED/HD Manual CSC Matrix Default Values Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 When the ED/HD manual CSC matrix adjust feature ...
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The hue adjust value is calculated using the following equation: Hue Adjust (°) = 0.17578125° ( HCR where HCR is the hue adjust control register (decimal). d For example, to adjust the hue by +4°, write 0x97 to the hue ...
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ADV7340/ADV7341 DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD; Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video but take ...
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SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction is ...
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ADV7340/ADV7341 ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7340/ADV7341: a sharpness filter mode and two adaptive filter modes. ED/HD Sharpness Filter Mode To enhance or ...
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CH1 500mV REF A 500mV 4.00µs Figure 73. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD sharpness ...
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ADV7340/ADV7341 Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A) When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 76 can be obtained. Figure 76. Output Signal from ED/HD ...
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DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values 0.5 in increments of 1/16. This factor ...
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ADV7340/ADV7341 LUM A CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 0 IRE VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED 100 IRE 87.5 IRE 50 IRE 12.5 IRE 0 IRE ...
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EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For synchronization purposes, the ADV7340/ADV7341 are able to accept either time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC , and ...
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ADV7340/ADV7341 , 1 2 Table 58. VSYNC Output Control ED/HD Sync ED/HD VSYNC ED/HD Input Output Sync Format Control Enable (Subaddress (Subaddress (Subaddress 0x30, Bit 2) 0x34, Bit 2) 0x02, Bit ...
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SLEEP MODE Subaddress 0x00, Bit 0 In sleep mode, most of the digital I/O pins of the ADV7340/ ADV7341 are disabled. For inputs, this means that the external data is ignored, and internally the logic normally driven by a given ...
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ADV7340/ADV7341 t SYNTTXOUT CVBS HSYNC 10.2µs TTX DATA TTX REQ TTX 10.2µs. SYNTTXOUT t = PIPELINE DELAY THROUGH ADV7340/ADC7341. PD TTX = TTX TO TTX (PROGRAMMABLE RANGE = 4 BITS [ PIXEL CLOCK ...
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PRINTED CIRCUIT BOARD LAYOUT AND DESIGN UNUSED PINS If the S_HSYNC , S_VSYNC , P_HSYNC , and P_VSYNC pins are not used, they should be tied to V through a pull-up resistor DD_IO (10 kΩ or 4.7 kΩ). Any other ...
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ADV7340/ADV7341 DAC OUTPUT 3 390nH 75Ω 300Ω 1 33pF 33pF 75Ω 4 Figure 88. Example of Output Filter for HD, 4× Oversampling CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 –40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M 10M 100M ...
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External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7340/ ADV7341 to minimize the possibility of noise pickup from neighboring circuitry and to minimize the effect of trace capacitance on ...
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ADV7340/ADV7341 TYPICAL APPLICATION CIRCUIT FERRITE BEAD V DD_IO 33µF 10µF GND_IO GND_IO FERRITE BEAD PV DD (1.8V) 33µF 10µF PGND PGND FERRITE BEAD V AA 33µF 10µF AGND AGND FERRITE BEAD V DD (1.8V) 33µF 10µF DGND DGND Y0 Y1 ...
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COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7340/ADV7341 support a copy generation manage- ment system (CGMS) conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd fields ...
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ADV7340/ADV7341 +100 IRE +70 IRE 0 IRE –40 IRE 11.2µs +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5µs ± 0.125µs +700mV 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns ...
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REF 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV START 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. Figure 98. Enhanced Definition (525p) CGMS Type B Waveform +700mV START ...
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ADV7340/ADV7341 SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7340/ADV7341 support wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is trans- mitted on Line 23. WSS data can be transmitted only when ...
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SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV7340/ADV7341 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields ...
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ADV7340/ADV7341 INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7340/ADV7341 are able to internally generate SD color bar and black bar test patterns. For this function MHz clock signal must be applied to the CLKIN_A pin. The register ...
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SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV7340/ADV7341are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. ...
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ADV7340/ADV7341 DISPLAY 622 623 624 625 H F EVEN FIELD DISPLAY 309 310 311 312 H ODD FIELD F ANALOG VIDEO H F VERTICAL BLANK ODD FIELD VERTICAL BLANK 318 313 314 315 316 ...
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Mode 1—Slave Option (Subaddress 0x8A = this mode, the ADV7340/ADV7341 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, ...
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ADV7340/ADV7341 Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV7340/ADV7341 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a ...
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DISPLAY 622 623 624 HSYNC VSYNC EVEN FIELD DISPLAY 309 310 311 HSYNC VSYNC ODD FIELD Mode 2—Master Option (Subaddress 0x8A = this mode, the ADV7340/ADV7341 can generate horizontal and vertical ...
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ADV7340/ADV7341 Mode 3—Master/Slave Option (Subaddress 0x8A = this mode, the ADV7340/ADV7341 accept or generate horizontal sync and odd/even field signals. When HSYNC ...
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HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 115. 1080i HSYNC and VSYNC ...
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ADV7340/ADV7341 VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 116. Y Levels—NTSC 700mV Figure 117. Pr Levels—NTSC 700mV Figure 118. Pb Levels—NTSC 700mV 300mV Figure 119. Y Levels—PAL 700mV Figure 120. Pr Levels—PAL ...
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ED/HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 122. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 ...
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ADV7340/ADV7341 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 127. ...
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SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72μs µ FRAMES ...
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ADV7340/ADV7341 VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 ...
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ACTIVE VIDEO 622 623 624 625 Figure 139. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 ...
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ADV7340/ADV7341 CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV7340/ ADV7341 for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 65 ...
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Table 68. 10-Bit 525i YCrCb In (EAV/SAV), RGB and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. ...
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ADV7340/ADV7341 Table 74. 10-Bit NTSC Square Pixel YCrCb In (EAV/SAV), CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. ...
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Table 80. 20-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz ...
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ADV7340/ADV7341 ENHANCED DEFINITION Table 86. ED Configuration Scripts 1 Input Format Input Data Width 525p at 59.94 Hz 10-bit DDR 525p at 59.94 Hz 10-bit DDR 525p at 59.94 Hz 10-bit DDR 525p at 59.94 Hz 10-bit DDR 525p at ...
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Table 89. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB ...
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ADV7340/ADV7341 Table 97. 30-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 ...
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Table 105. 20-Bit 625p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x18 625p at 50 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. ...
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ADV7340/ADV7341 HIGH DEFINITION Table 113. HD Configuration Scripts Input Format Input Data Width 720p at 60 Hz/59.94 Hz 10-bit DDR 720p at 60 Hz/59.94 Hz 10-bit DDR 720p at 60 Hz/59.94 Hz 10-bit DDR 720p at 60 Hz/59.94 Hz 10-bit ...
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Table 116. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB ...
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ADV7340/ADV7341 Table 124. 30-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 ...
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Table 132. 20-Bit 1080i YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x68 1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 2 ADV7340BSTZ −40°C to +85°C 2 ADV7341BSTZ −40°C to +85°C EVAL-ADV7340EBZ 2 2 EVAL-ADV7341EBZ 1 Macrovision-enabled ICs require the buyer approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video RoHS Compliant Part. ...