ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 86
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ADV7341BSTZ
Manufacturer Part Number
ADV7341BSTZ
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADV7341BSTZ.pdf
(108 pages)
Specifications of ADV7341BSTZ
Number Of Dac's
6
Adc/dac Resolution
12b
Screening Level
Industrial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Compliant
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Quantity
Price
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ADV7340/ADV7341
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7340/ADV7341 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as
required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and
FIELD are output on the S_HSYNC and S_VSYNC pins, respectively.
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7340/ADV7341 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV7340/ADV7341 automatically blank all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input
on the S_HSYNC and S_VSYNC pins, respectively.
HSYNC
HSYNC
VSYNC
VSYNC
522
DISPLAY
260
DISPLAY
HSYNC
523
FIELD
PIXEL
DATA
261
524
262
525
263
Figure 108. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
1
264
EVEN FIELD
ODD FIELD
2
265
3
266
Figure 109. SD Slave Mode 2, NTSC
4
267
Rev. A | Page 86 of 108
5
VERTICAL BLANK
268
VERTICAL BLANK
6
269
EVEN FIELD
ODD FIELD
7
270
8
271
9
272
NTSC = 122 × CLOCK/2
PAL = 132 × CLOCK/2
10
273
11
Cb
274
Y
Cr
20
283
Y
21
284
DISPLAY
DISPLAY
22
285