HIP0081AS1 Intersil, HIP0081AS1 Datasheet - Page 6
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HIP0081AS1
Manufacturer Part Number
HIP0081AS1
Description
Manufacturer
Intersil
Datasheet
1.HIP0081AS1.pdf
(14 pages)
Specifications of HIP0081AS1
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Diagnostic Interface Overview
Each Quad Inverting Power Driver IC may be used as a single
power switching driver, with or without the diagnostic interface.
Where more than 4 Power Driver Switches are required, the
HIP0080 or HIP0081 may be used in a multiple IC cascade
connection. In cascade operation, the diagnostic data from all
chips is read as a single serial sequence of fault bits. As shown
in the Functional Block Diagram each output stage has voltage
and temperature sensors to detect fault conditions while
comparators and delay filters process the data. Four bits of
diagnostic information is provided as fault feedback from each
of the four output stages. When detected, the diagnostic data is
put in a parallel diagnostic data register. Using the diagnostic
control interface to address the system (one or more ICs in
cascade), the fault data is transferred from the parallel
diagnostic data register to a serial diagnostic data register as a
sequence of 16 bits for each IC.
All diagnostic data bits may be read using the Chip Select (CS)
and the Clock (CLK) inputs. The CLK input must be low, when
CS goes active low. After reading the first bit at DO to
determine if there is an error flag, the following 16 bits of serial
diagnostic data may be clocked out of DO. Clocking the CLK
input synchronously shifts the serial register data out of DO
while cascaded data (from other devices or sources) is shifted
into the DI input. As data is shifted out of DO, the parallel
diagnostic data register is cleared on the first rising edge of the
CLK input, following the CS low. After each 16 clocks,
cascaded diagnostic data from the next IC in sequence is then
shifted out of the DO output. Shifting the serial diagnostic data
out of DO is done as a continuous sequence, reading the data
from all ICs in cascade while CS remains low. New diagnostic
data can be stored in the parallel diagnostic data registers on
each IC while the existing serial diagnostic data is read.
Referring to Figure 1 and Figure 2, there are two sources that
generate an OR’ed Fault Flag at DO when CS goes low. The
two fault data sources are (1) the on-chip fault detection and (2)
the off-chip DI input from front end ICs in the cascade. The fault
data bit, labeled DF (Data Fault) in Figure 2, contains the OR’ed
inputs from both sources. The DF bit is not part of the 16-bit
serial diagnostic data sequence. In cascaded operation, the DI
input for the first of the selected chips should be tied low. And,
in single IC operation (no cascade), the DI input should also be
tied low. In cascaded operation, the Error Flags are cascaded
via the DI inputs.
The on-chip fault Error Flag goes high if any one of the 16
diagnostic data fault bits have been set HIGH. This fault Error
Flag bit precedes the 16 diagnostic data fault bits and is OR’ed
with all diagnostic data fault bits. The DF bit flags the presence
of an Error Flag fault on the IC and in any part of the cascaded
string, including DI data input. As shown in Figure 3 each IC in
the cascade provides an output which is passed to the DI input
of the following IC and is passed on as an OR’ed bit to the DO
output of the last IC in the cascade. A fault condition is
immediately evident without reading all diagnostic data bits.
6
HIP0080, HIP0081
However, all bits must be read to determine which chip and
which diagnostic bit has been set. The Fault Flag is reset by the
CLK input when the bits are read. When no fault condition is
detected, it is not necessary to toggle the CLK input. When a
fault is detected, at least one toggle of the clock is needed to
reset the parallel diagnostic register which clears the register of
all detected fault states.
The last IC in the string ORs its own 16 fault bits in the parallel
diagnostic register data and sends this data bit to an Error Flag
register. The Error Flag register outputs the presence of a fault
in one or more bits of the parallel diagnostic data register. As
shown in Figure 2, the Error Flag is the first bit in front of the
serial register and is input to OR Gate, U7 with the DI input. The
DI input passes through AND Gate, U6 when the GATE signal
is high and output via the amplifier U8 to DO. The output
amplifier U8 is active only while CS is low. When CS is low, the
RS Flip-Flop drives the GATE output high. When the GATE is
high, the cascaded DF bits are jammed from DI to DO. All Error
Flags in the cascade are cleared (by the CLK input) when the
serial diagnostic data is clocked out of DO.
The GATE is an internal control signal that is forced high when
the CLK input is low and CS goes low. The GATE will remain
high, even when CS is returned to a high state, provided the
CLK input has not changed from a low state. This condition still
applies when fault data is detected. The DO output is not
latched; however, the Error Flag is latched when CS goes low
and will not be updated until the next time CS goes low. The
fault data is preserved as long as the CLK input does not go
high. If the CLK is high when CS goes low, the GATE will be
disabled and no cascade data will be shifted from DI to DO.
Under normal conditions, the CLK signal goes high to switch
the GATE low and simultaneously shifts the first of 16
diagnostic data bits out of the serial diagnostic data register to
DO. The CS low input is not latched and must be held low while
all data is shifted out of DO.
The diagnostic interfaces to the HIP0080 and HIP0081 are SPI
compatible. The microcontroller is programmed to control the
read and respond action based on the diagnostic readout.
Normally the CS input is addressed and DO is read. If a fault is
indicated by the Error Flag, all data is shifted out of DO and
processed to determine the diagnostic fault condition. The Error
Flag bit does require a separate input back to the
microcontroller to initiate the serial data shift. When the CLK
signal starts, the serial sequence starting with the first of the 16
serial diagnostic bits is input to the microcontroller.
Serial Register Data Sequence
The fault data follows the Serial Register Data Sequence of
Table 1 in bit sequence and, in cascade, by IC sequence. In
each of the 4 power switching output channels, the
diagnostic sense circuits set 1-bit in the parallel diagnostic
register for each of the 4 diagnostics fault conditions. A total
of 16 diagnostics data bits are shifted to the serial register
when CS goes low. Table 1 shows the order and sequence