MC33911G5ACR2 Freescale, MC33911G5ACR2 Datasheet - Page 85

• Manufacturer Part Number: MC33911G5ACR2
• Manufacturer: Freescale

Specifications of MC33911G5ACR2

• Turn Off Delay Time: 10us
• Number Of Drivers: 2
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Lead Free Status / RoHS Status: Compliant

Timing Control Register - TIMCR
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
CS/WD - Cyclic Sense or Watchdog prescaler select.
to, the Cyclic Sense prescaler or the watchdog prescaler.
WDx - Watchdog Prescaler
prescaler and therefore selects the watchdog period in
accordance with
windowing watchdog is active.
Table 54.
CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
85
33911
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WD2
This register is a double purpose register which allows to
This write-only bit selects which prescaler is being written
1 = Cyclic Sense Prescaler selected
0 = watchdog Prescaler select
This write-only bits selects the divider for the watchdog
This write-only bits selects the interval for the wake-up
0
0
0
0
1
1
1
1
Table 53. Timing Control Register - $A
Condition
Reset
Reset
Value
Write
Watchdog Prescaler
WD1
0
0
1
1
0
0
1
1
Table
CS/WD
C3
-
-
WD0
0
1
0
1
0
1
0
1
54. This configuration is valid only if
CYST2
WD2
C2
0
Prescaler Divider
CYST1
WD1
POR
C1
0
10
12
14
1
2
4
6
8
CYST0
WD0
C0
0
Configuration Register (CFR) (see
CFR).
when entering in Stop or Sleep mode. Otherwise a timed
wake-up is performed after the period shown in
Table 55.
Watchdog Status Register - WDSR
is also returned when writing to the TIMCR.
WDTO - Watchdog Timeout
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
WDTO bit.
Notes
CYSX8
127.
This option is only active if the high side switch is enabled
This register returns the watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the TIMCR will clear the
1 = Last reset caused by watchdog timeout
0 = None
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
(127)
bit CYSX8 is located in Configuration Register (CFR)
Table 56. Watchdog Status Register - $A/$B
Read
Cyclic Sense Interval
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
Analog Integrated Circuit Device Data
CYST1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
Freescale Semiconductor
Configuration Register -
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No cyclic sense
WDWO
S0
Table
Interval
1120ms
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
20ms
40ms
60ms
80ms
55.