XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 195
XC5VLX50-1FFG676I
Manufacturer Part Number
XC5VLX50-1FFG676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
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- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Multiplexers
delay to access the LUT. This operation is asynchronous and independent of the clock and
clock-enable signals.
Static Read Operation
If the 5-bit address is fixed, the Q output always uses the same bit position. This mode
implements any shift-register length from 1 to 32 bits in one LUT. The shift register length
is (N+1), where N is the input address (0 – 31).
The Q output changes synchronously with each shift operation. The previous bit is shifted
to the next position and appears on the Q output.
Shift Register Summary
•
•
•
•
•
•
Function generators and associated multiplexers in Virtex-5 FPGAs can implement the
following:
•
•
•
These wide input multiplexers are implemented in one level or logic (or LUT) using the
dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow LUT
combinations of up to four LUTs in a slice.
A shift operation requires one clock edge.
Dynamic-length read operations are asynchronous (Q output).
Static-length read operations are synchronous (Q output).
The data input has a setup-to-clock timing specification.
In a cascadable configuration, the Q31 output always contains the last bit value.
The Q31 output changes synchronously after each shift operation.
4:1 multiplexers using one LUT
8:1 multiplexers using two LUTs
16:1 multiplexers using four LUTs
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CLB Overview
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