XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 47
XC5VLX50-1FFG676I
Manufacturer Part Number
XC5VLX50-1FFG676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FFG676I
Manufacturer:
XILINX
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Company:
Part Number:
XC5VLX50-1FFG676I
Manufacturer:
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Quantity:
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- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
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- Download datasheet (14Mb)
Clock Management Technology
Clock Management Summary
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The Clock Management Tiles (CMTs) in the Virtex-5 family provide very flexible, high-
performance clocking. Each CMT contains two DCMs and one PLL.
simplified view of the center column resources including the CMT block, where the DCM
is located. Each CMT block contains two DCMs and one PLL.
X-Ref Target - Figure 2-1
www.xilinx.com
(Bottom Half DCMs/PLLs)
Figure 2-1: CMT Location
(Top Half DCMs/PLLs)
(Larger Devices Only)
(Larger Devices Only)
Config Blocks and
(Bottom Half)
(Bottom Half)
CMT Blocks
CMT Blocks
Config I/O
Config I/O
I/O Banks
(Top Half)
(Top Half)
I/O Banks
Clock I/O
Clock I/O
BUFGs
Center Column
Virtex-5 FPGA
UG190_c2_01_022609
Chapter 2
Figure 2-1
shows a
47
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