XC5VLX50-1FFG676I Xilinx Inc, XC5VLX50-1FFG676I Datasheet - Page 51
XC5VLX50-1FFG676I
Manufacturer Part Number
XC5VLX50-1FFG676I
Description
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG676I
Package
676FCBGA
Family Name
Virtex®-5
Device Logic Units
46080
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
440
Ram Bits
1769472
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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DCM Ports
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DCM_ADV Primitive
DCM Clock Input Ports
Source Clock Input - CLKIN
The DCM_ADV primitive has access to all DCM features and ports available in
DCM_BASE plus additional ports for the dynamic reconfiguration feature. It is a superset
of the DCM_BASE primitive. DCM_ADV uses all the DCM features including clock
deskew, frequency synthesis, fixed or variable phase shifting, and dynamic
reconfiguration.
Table 2-3: DCM_ADV Primitive
There are four types of DCM ports available in the Virtex-5 architecture:
•
•
•
•
The source clock (CLKIN) input pin provides the source clock to the DCM. The CLKIN
frequency must fall in the ranges specified in the Virtex-5 FPGA Data Sheet. If CLKIN is
stopped for 100 ms or longer, the DCM powers down. The clock input signal comes from
one of these buffers:
1.
2.
3.
4.
Clock Input
Control and Data Input
Clock Output
Status and Data Output
DCM Clock Input Ports
DCM Control and Data Input Ports
DCM Clock Output Ports
DCM Status and Data Output Ports
IBUFG – Global Clock Input Buffer
The DCM compensates for the clock input path when CLKFB is connected and an
IBUFG on the same half (top or bottom) of the device as the DCM is used.
BUFGCTRL – Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-5 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
PLL – Phase-Locked Loop
A PLL block within the same CMT can drive the CLKIN input of either DCM in the
CMT block. No global buffer is required in between. See
page 75
IBUF – Input Buffer
When an IBUF drives the CLKIN input, the PAD to DCM input skew is not
compensated.
Available Ports
for more information.
Table 2-3
www.xilinx.com
lists the available ports in the DCM_ADV primitive.
CLKIN, CLKFB, PSCLK, DCLK
RST, PSINCDEC, PSEN, DADDR[6:0], DI[15:0], DWE, DEN
CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, CLKFX180
LOCKED, PSDONE, DO[15:0], DRDY
Port Names
Application Examples,
DCM Ports
51
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