AD9854ASQ Analog Devices Inc, AD9854ASQ Datasheet - Page 28

• Manufacturer Part Number: AD9854ASQ
• Manufacturer: Analog Devices Inc

Specifications of AD9854ASQ

• Lead Free Status / RoHS Status: Not Compliant

AD9854
USING THE AD9854
INTERNAL AND EXTERNAL UPDATE CLOCK
This update clock function is comprised of a bidirectional
I/O pin, Pin 20, and a programmable 32-bit down-counter. To
program changes that are to be transferred from the I/O buffer
registers to the active core of the DDS, a clock signal (low-to-
high edge) must be externally supplied to Pin 20 or internally
generated by the 32-bit update clock.
When the user provides an external update clock, it is internally
synchronized with the system clock to prevent a partial transfer
of program register information due to a violation of data set up
or hold time. This mode allows the user to completely control when
updated program information becomes effective. The default
mode for the update clock is internal (the internal update clock
control register bit is logic high). To switch to external update
clock mode, the internal update clock control register bit must
be set to logic low. The internal update mode generates automatic,
periodic update pulses at intervals set by the user.
An internally generated update clock can be established by
programming the 32-bit update clock registers (Addresses 16 to
19 hex) and setting the internal update clock control register bit
(Address 1F hex) to logic high. The update clock down-counter
function operates at half the rate of the system clock (150 MHz
maximum) and counts down from a 32-bit binary value (pro-
grammed by the user). When the count reaches 0, an automatic
I/O update of the DDS output or functions is generated. The
update clock is internally and externally routed to Pin 20 to
allow users to synchronize the programming of update
information with the update clock rate. The time between
update pulses is given as
where N is the 32-bit value programmed by the user.
The allowable range of N is from 1 to (2
generated update pulse that is output from Pin 20 has a fixed
high time of eight system clock cycles.
Programming the update clock register to a value less than five
causes the I/O UD CLK pin to remain high. Although the update
clock can function in this state, it cannot be used to indicate when
data is transferring. This is an effect of the minimum high pulse
time when I/O UD CLK functions as an output.
(N + 1) × (System Clock Period × 2)
32
− 1). The internally
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ON/OFF OUTPUT SHAPED KEYING (OSK)
This feature allows the user to control the amplitude vs. time
slope of the I and Q DAC output signals. This function is used
in burst transmissions of digital data to reduce the adverse
spectral impact of short, abrupt bursts of data. Users must
first enable the digital multipliers by setting the OSK EN bit
(Control Register Address 20 hex) to logic high in the control
register. Otherwise, if the OSK EN bit is set low, the digital
multipliers responsible for amplitude control are bypassed and
the I and Q DAC outputs are set to full-scale amplitude. In
addition to setting the OSK EN bit, a second control bit, OSK
INT (also at Address 20 hex), must be set to logic high. Logic
high selects the linear internal control of the output ramp-up or
ramp-down function. A logic low in the OSK INT bit switches
control of the digital multipliers to user-programmable 12-bit
registers, allowing users to dynamically shape the amplitude
transition in practically any fashion. These 12-bit registers,
labeled Output Shape Key I and Output Shape Key Q, are
located at Addresses 21 through 24 hex, as listed in Table 7. The
maximum output amplitude is a function of the R
and is not programmable when OSK INT is enabled.
The transition time from zero scale to full scale must also be
programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the
programmable 8-bit ramp rate counter. This is a down-counter
that is clocked at the system clock rate (300 MHz maximum)
and that generates one pulse whenever the counter reaches 0.
This pulse is routed to a 12-bit counter that increments with
each pulse received. The outputs of the 12-bit counter are
connected to the 12-bit digital multiplier. When the digital
multiplier has a value of all 0s at its inputs, the input signal is
multiplied by 0, producing zero scale. When the multiplier has a
value of all 1s, the input signal is multiplied by a value of 4095
or 4096, producing nearly full scale. There are 4094 remaining
fractional multiplier values that produce output amplitudes
scaled according to their binary values.
SCALE
SCALE
ZERO
ZERO
Figure 49. Shaped On/Off Keying
SHAPED ON/OFF KEYING
ABRUPT ON/OFF KEYING
SET
resistor
FULL
SCALE
FULL
SCALE