LTC4210-4IS6#PBF Linear Technology, LTC4210-4IS6#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC4210-4IS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4210-4IS6#PBF

• Linear Misc Type: Positive Low Voltage
• Package Type: TSOT-23
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 7V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

APPLICATIO S I FOR ATIO
LTC4210-3/LTC4210-4
power-up or during current limiting. The first type of oscil-
lation occurs at high frequencies, typically above 1MHz.
This high frequency oscillation is easily damped with R
mentioned in method 2.
The second type of oscillation occurs at frequencies
between 200kHz and 800kHz due to the load capacitance
being between 0.2µF and 9µF, the presence of R
resistance, the absence of a drain bypass capacitor, a
combination of bus wiring inductance and bus supply output
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load
capacitance below 10µF™, the second choice is connect-
ing an external C
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance C
determines the GATE start-up as in Equation 6. The C
should be kept below 0.15µF at high supply operation as
the capacitive energy ( 0.5 • C
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is serving during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, C
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
The 100µA is a nonideal current source approximating a 7k
resistor below 0.4V.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply V
point 1 of Figure 3. The LTC4210 is in reset mode as the ON
10
5µA pull-up
60µA pull-up
2µA pull-down
100µA pull-down
P
> 1.5nF.
U
TIMER
U
. There are two comparator
GATE
• V
W
GATE
2
) is discharged
U
GATE
IN
G
and R
at time
GATE
also
G
as
C
pin is low. GATE is pulled low and the TIMER pin is pulled
low with a 100µA source. At time point 2, the short pin
makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5µA. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
ends. The 100µA current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
C
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
Start-Up Cycle Without Current Limit
The GATE is released with a 10µA pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold V
TIMER
t
INITIAL
V
V
TIMER
V
GATE
V
OUT
V
ON
IN
by equation:
≈ 272.9 • C
RESET
>2.5V
MODE
Figure 3. Normal Operating Sequence
>1.3V
1
2
INITIAL
CYCLE
5µA
TIMER
TH
3 4 5
and V
START-UP
COMP2
10µA
100µA
CYCLE
COMP1
ms/µF
V
TH
OUT
6
NORMAL
CYCLE
starts to follow the
7
4210 F03
DISCHARGE
BY LOAD
421034fa
(5)