LTC4210-4IS6#PBF Linear Technology, LTC4210-4IS6#PBF Datasheet - Page 9

• Manufacturer Part Number: LTC4210-4IS6#PBF
• Manufacturer: Linear Technology

Specifications of LTC4210-4IS6#PBF

• Linear Misc Type: Positive Low Voltage
• Package Type: TSOT-23
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 7V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Height (mm): 0.9mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

APPLICATIO S I FOR ATIO
Calculating Current Limit
For a selected R
Equation 1. The minimum load current is given by
Equation 2:
where
The maximum load current is given by Equation 3:
where
If a 7mΩ sense resistor with ±1% tolerance is used for
current limiting, the nominal current limit is 7.14A.
From Equations 2 and 3, I
I
current limit must exceed the circuit maximum operat-
ing load current with margin. The sense resistor power
rating must exceed V
Frequency Compensation
A compensation circuit should be connected to the GATE
pin for current limit loop stability.
Method 1
The simplest frequency compensation network consists
of R
Generally, the compensation value in Figure 2a is suffi-
cient for a pair of input wires less than a foot in length.
Applications with longer input wires may require the R
C
mance. For a pair of three foot input wires, users can start
LIMIT(MAX)
C
C
I
R
I
R
value to be increased for better fault transient perfor-
LIMIT MIN
LIMIT MAX
GATE
C
SENSE MAX
SENSE MIN
and C
(
(
= C
(
(
= 8.08A. For proper operation, the minimum
C
)
ISS
)
(Figure 2a). The total GATE capacitance is:
=
=
)
)
SENSE
=
R
+ C
=
R
SENSE MAX
R
R
SENSE MIN
V
V
SENSE
U
CB MIN
CB MAX
C
SENSE
, the nominal load current is given by
(
(
CB(MAX)
(
(
U
•
)
•
)
⎛
⎝ ⎜
⎛
⎝ ⎜
)
)
1
1
=
=
–
+
2
LIMIT(MIN)
/R
R
R
R
R
100
100
TOL
SENSE
SENSE
SENSE(MIN)
TOL
W
56
44
⎞
⎠ ⎟
mV
mV
⎞
⎠ ⎟
(
(
M M AX)
M M IN)
= 6.22A and
.
U
C
(2)
(3)
(4)
or
with C
general rule for AC stability required is C
1kΩ.
Method 2
The compensation network in Figure 2b is similar to the
circuitry used in method 1 but with an additional gate
resistor R
frequency parasitic oscillations frequently associated with
the power MOSFET. In some applications, the user may
find that R
well. However, too large of an R
turn-off time. The recommended R
and 500Ω. R
internal zener clamp during transient events. The recom-
mended R
parasitic compensation capacitor C
< load capacitance C
Parasitic MOSFET Oscillation
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping at
C
= 47nF and R
12V
V
V
5V
IN
IN
C
G
G
and C
. The R
G
helps in short-circuit transient recovery as
Figure 2. Frequency Compensation
V
V
Method 2
Method 1
CC
CC
limits the current flow into the GATE pin’s
LTC4210*
LTC4210*
6
6
R
0.007Ω
R
0.007Ω
LTC4210-3/LTC4210-4
(2b)
(2a)
SENSE
SENSE
C
values are the same as method 1. The
SENSE
SENSE
C
G
L
GATE
GATE
= 100Ω. Despite the wire length, the
5
< 9µF, otherwise it is optional.
5
resistor helps to minimize high
Si4410DY
Si4410DY
4
4
Q1
Q1
R
200Ω
R
100Ω
R
100Ω
4210 F02
G
C
C
C
10nF
C
10nF
G
C
C
+
value will slow down the
P
G
is required when 0.2µF
C
range is between 5Ω
L
**USE C
**USE
C
2.2nF
V
*ADDITIONAL DETAILS
*ADDI
P
OUT
OMITTED FOR CLARITY
OTHERWISE NOT REQUIRED
OMIT
OTHE
**
C
+
≥ 8nF and R
P
IF 0.2µF < C
C
L
V
OUT
L
421034fa
< 9µF,
9
C
≤