MMA8451QR1 Freescale, MMA8451QR1 Datasheet - Page 49

• Manufacturer Part Number: MMA8451QR1
• Manufacturer: Freescale

Specifications of MMA8451QR1

• Lead Free Status / RoHS Status: Compliant

Table 73. MMA8451Q Register Map
48
MMA8451Q
Reg
0A
0B
0C
0D
0E
0F
1D
1E
1F
2A
2B
2C
2D
2E
2F
00
01
02
03
04
05
06
09
10
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
HP_FILTER_CUTOFF
TRANSIENT_COUNT
STATUS/F_STATUS
TRANSIENT_CFG
TRANSIENT_SRC
TRANSIENT_THS
XYZ_DATA_CFG
FF_MT_COUNT
PL_BF_ZCOMP
P_L_THS_REG
ASLP_COUNT
INT_SOURCE
PULSE_THSX
PULSE_THSY
PULSE_THSZ
PULSE_TMLT
PULSE_LTCY
PULSE_WIND
OUT_X_MSB
OUT_Y_MSB
OUT_Z_MSB
FF_MT_CFG
FF_MT_SRC
PULSE_CFG
PULSE_SRC
CTRL_REG1
CTRL_REG2
CTRL_REG3
CTRL_REG4
CTRL_REG5
OUT_X_LSB
OUT_Y_LSB
OUT_Z_LSB
PL_STATUS
FF_MT_THS
WHO_AM_I
PL_COUNT
TRIG_CFG
F_SETUP
SYSMOD
PL_CFG
OFF_X
OFF_Y
OFF_Z
Name
Freefall/Motion Debounce
Freefall/Motion Threshold
Transient Threshold R/W
(Interrupt Configuration)
Pulse X Threshold R/W
Pulse Y Threshold R/W
Pulse Z Threshold R/W
PL Back/Front Z Comp
Freefall/Motion Source
(WAKE Interrupts from
(Interrupt Enable Map)
PL THRESHOLD R/W
Freefall/Motion Config
Pulse First Timer R/W
HP Filter Setting R/W
PL Configuration R/W
Transient Config R/W
Auto-SLEEP Counter
PL DEBOUNCE R/W
Transient Debounce
Transient Source R
Pulse Latency R/W
FIFO Triggers R/W
Pulse 2nd Window
Control Reg1 R/W
Control Reg2 R/W
Interrupt Status R
Pulse Config R/W
X 8-bit offset R/W
Y 8-bit offset R/W
Z 8-bit offset R/W
FIFO Set-up R/W
Data Config R/W
System Mode R
14 bit X Data R
14 bit X Data R
14 bit Y Data R
14 bit Y Data R
Pulse Source R
14 bit Z Data R
14 bit Z Data R
Data Status R
ID Register R
Control Reg3
Control Reg4
Control Reg5
SLEEP) R/W
PL Status R
Definition
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
INT_CFG_ASLP
INT_EN_ASLP
ASLP_RATE1
FIFO_GATE
P_L_THS[4]
SRC_ASLP
F_MODE1
DBNCE[7]
DBCNTM
DBCNTM
DBCNTM
BKFR[1]
ZYXOW
NEWLP
FGERR
TMLT7
LTCY7
WIND7
XD13
YD13
ZD13
Bit 7
XD5
YD5
ZD5
ELE
DPA
EA
D7
D7
EA
D7
ST
D7
D7
D7
—
—
—
—
—
—
—
—
0
INT_CFG_FIFO
WAKE_TRANS
ASLP_RATE0
INT_EN_FIFO
P_L_THS[3]
SRC_FIFO
F_MODE0
DBNCE[6]
BKFR[0]
PL_EN
THSX6
THSY6
THSZ6
TMLT6
WIND6
FGT_4
LTCY6
XD12
YD12
ZD12
THS6
THS6
Bit 6
ZOW
XD4
YD4
OAE
RST
ZD4
ELE
AxZ
LO
D6
EA
D6
D6
D6
D6
D6
—
—
—
—
—
0
INT_CFG_TRANS
Pulse_HPF_BYP
WAKE_LNDPRT
INT_EN_TRANS
SRC_TRANS
Trig_TRANS
P_L_THS[2]
F_WMRK5
DBNCE[5]
ZTRANSE
ZDPEFE
FGT_3
THSX5
THSY5
THSZ5
TMLT5
LTCY5
WIND5
YOW
XD11
YD11
ZD11
ZEFE
THS5
THS5
Bit 5
XD3
YD3
ZD3
ZHE
DR2
AxY
D5
D5
D5
D5
D5
D5
—
—
—
—
—
—
0
INT_CFG_LNDPRT
INT_EN_LNDPRT
Pulse_LPF_EN
SRC_LNDPRT
WAKE_PULSE
Trig_LNDPRT
Z_Trans_Pol
P_L_THS[1]
F_WMRK4
DBNCE[4]
SMODS1
HPF_Out
ZSPEFE
THSX4
THSY4
WIND4
FGT_2
THSZ4
TMLT4
LTCY4
XD10
YD10
YEFE
THS4
THS4
XOW
ZD10
Bit 4
ZHP
DR1
XD2
YD2
ZD2
ELE
AxX
D4
D4
D4
D4
D4
D4
—
—
—
1
INT_CFG_PULSE
INT_EN_PULSE
WAKE_FF_MT
SRC_PULSE
Trig_PULSE
P_L_THS[0]
F_WMRK3
DBNCE[3]
YTRANSE
SMODS0
YDPEFE
ZYXDR
ZTEFE
THSX3
THSY3
THSZ3
TMLT3
WIND3
FGT_1
LTCY3
XEFE
THS3
THS3
Bit 3
XD9
XD1
YD9
YD1
YHE
DPE
DR0
ZD9
ZD1
D3
D3
D3
D3
D3
D3
—
—
—
—
—
1
INT_CFG_FF_MT
INT_EN_FF_MT
SRC_FF_MT
Y_Trans_Pol
Trig_FF_MT
F_WMRK2
DBNCE[2]
ZLOCK[2]
YSPEFE
LAPO[1]
LNOISE
YTEFE
THSX2
THSY2
FGT_0
HYS[2]
THSZ2
TMLT2
LTCY2
WIND2
THS2
THS2
Pol_Z
SLPE
Bit 2
ZDR
YHP
XD8
XD0
YD8
YD0
ZD8
ZD0
D2
D2
D2
D2
D2
D2
—
—
—
—
—
0
Freescale Semiconductor
F_WMRK1
SYSMOD1
DBNCE[1]
XTRANSE
ZLOCK[1]
XDPEFE
F_READ
LAPO[0]
MODS1
HYS[1]
XTEFE
THSX1
THSY1
THSZ1
TMLT1
LTCY1
WIND1
Pol_Y
SEL1
THS1
THS1
Bit 1
IPOL
YDR
XD7
YD7
XHE
ZD7
FS1
D1
D1
D1
D1
D1
D1
—
—
—
—
—
—
0
0
0
1
INT_CFG_DRDY
INT_EN_DRDY
X_Trans_Pol
SRC_DRDY
F_WMRK0
SYSMOD0
Sensors
DBNCE[0]
ZLOCK[0]
HPF_BYP
XSPEFE
ACTIVE
MODS0
BAFRO
THSX0
THSY0
WIND0
PP_OD
HYS[0]
THSZ0
TMLT0
LTCY0
THS0
THS0
Pol_X
SEL0
Bit 0
XDR
XHP
XD6
YD6
ZD6
FS0
D0
D0
D0
D0
D0
D0
—
—
—
0
0
0
0