S71PL064JB0BFW0B0 Spansion Inc., S71PL064JB0BFW0B0 Datasheet - Page 23

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S71PL064JB0BFW0B0

Manufacturer Part Number
S71PL064JB0BFW0B0
Description
Manufacturer
Spansion Inc.
Datasheet

Specifications of S71PL064JB0BFW0B0

Operating Supply Voltage (max)
3.1V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
MCP
128/128/64/32 Megabit (8/4/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory with Enhanced VersatileIO
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128/64/32Mbit Page Mode devices
— Page size of 8 words: Fast page read access from
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
FlexBank Architecture (PL127J/PL064J/PL032J)
— 4 separate banks, with up to two simultaneous
— Bank A:
— Bank B:
— Bank C:
— Bank D:
Enhanced VersatileI/O
— Output voltage generated and input voltages
— V
— 3V V
random locations within the page
program operations for battery-powered applications
executing erase/program functions in another bank
operations per device
PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7)
PL127J - 48Mbit (32 Kw x 96)
PL064J - 24Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
PL127J - 48Mbit (32 Kw x 96)
PL064J - 24Mbit (32 Kw x 48)
PL032J - 12 Mbit (32 Kw x 24)
PL127J -16Mbit (4 Kw x 8 and 32 Kw x 31)
PL064J - 8Mbit (4 Kw x 8 and 32 Kw x 15)
PL032J - 4Mbit (4 Kw x 8 and 32 Kw x 7)
tolerated on all control inputs and I/Os is determined
by the voltage on the V
IO
options at 1.8 V and 3 V I/O for PL127J devices
IO
for PL064J and PL032J devices
Publication Number S29PL127_064_032J_00_
TM
IO
(V
pin
IO
) Control
Revision A
PERFORMANCE CHARACTERISTICS
SOFTWARE FEATURES
SecSi
— Up to 128 words accessible through a command
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 110 nm process technology
Data Retention: 20 years typical
Cycling Endurance: 1 million cycles per sector
typical
High Performance
— Page access times as fast as 20 ns
— Random access times as fast as 55 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 17 mA program/erase current
— 0.2 µA typical standby mode current
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F, Am29LV, Am29DL,
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
Unlock Bypass Program command
— Reduces overall programming time when issuing
TM
Amendment 1
sequence
and AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
allowing host software to easily reconfigure for
different Flash devices
operations in other sectors of same bank
multiple program command sequences
Control
TM
(Secured Silicon) Sector region
Issue Date May 21, 2004
PRELIMINARY

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