RD28F1602C3B70 Intel, RD28F1602C3B70 Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
RD28F1602C3B70
Manufacturer Part Number
RD28F1602C3B70
Description
Manufacturer
Intel
Datasheet
1.RD28F1602C3B70.pdf
(75 pages)
Specifications of RD28F1602C3B70
Operating Supply Voltage (max)
3.3V
Operating Temperature (max)
85C
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant
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C3 SCSP Flash Memory
2.1.1
Table 3.
2.1.2
26 Aug 2005
12
Notes:
1.
2.
Read
Write
Standby
Output Disable
Reset
Read
Write
Standby
Output Disable
Data Retention
Two devices cannot drive the memory bus at the same time.
To place the SRAM into data retention mode, lower the S-V
Modes
Read
The flash memory device provides four read modes:
These flash memory read modes do not depend on the F-V
or after exit from reset, the flash memory device automatically defaults to read array mode. F-CE#
and F-OE# must be asserted to obtain data from the flash memory device.
The SRAM provides only one read mode. S-CS1#, S-CS2, and S-OE# must be asserted to obtain
data from the SRAM device. See
Intel Advanced+ Boot Block Flash Memory SCSP Bus Operations
Output Disable
When F-OE# and S-OE# are deasserted, the SCSP output signals are placed in a high-impedance
state.
•
•
•
•
Read array
Read identifier
Read status
CFI query
Intel
Any FLASH mode is allowable
H
H
H
H
L
FLASH must be in High Z
®
Advanced+ Boot Block Flash Memory (C3) SCSP Family
Flash Signals
H
X
L
L
L
Order Number: 252636, Revision: 004
H
X
H
X
L
H
H
L
X
X
Table 3
H
X
L
L
L
for a summary of operations.
Any SRAM mode is allowable
SRAM must be in High Z
same as a standby
CC
SRAM Signals
H
H
H
X
L
signal to the V
PP
H
X
X
H
L
voltage. Upon initial device power-up
DR
H
X
X
H
L
range, as specified.
L
L
X
X
X
Memory Output
SRAM
SRAM
Flash
Flash
Other
Other
Other
Other
Other
Other
High Z
High Z
High Z
High Z
High Z
High Z
D
D
D
D
D
D
OUT
OUT
0
15
IN
IN
–
Datasheet
Notes
2,3,4
4,5,6
4,5,6
4,5,7
2,4
5,6
5,6
5,6
2,4
2,4
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