CY7C4231-15AC Cypress Semiconductor Corp, CY7C4231-15AC Datasheet

CY7C4231-15AC

Manufacturer Part Number
CY7C4231-15AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4231-15AC

Configuration
Dual
Density
16Kb
Access Time (max)
10ns
Word Size
9b
Organization
2Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-06016 Rev. *C
Features
• High-speed, low-power, First-In, First-Out (FIFO)
• High-speed 100-MHz operation (10 ns Read/Write cycle
• Low power (I
• Fully asynchronous and simultaneous Read and Write
• Empty, Full, and Programmable Almost Empty and
• TTL-compatible
• Expandable in width
• Output Enable (OE) pin
• Independent Read and Write enable pins
• Center power and ground pins for reduced noise
• Width-expansion capability
• Space saving 7 mm × 7 mm 32-pin TQFP
• Pin-compatible and functionally equivalent to
Logic Block Diagram
memories
— 64 × 9 (CY7C4421)
— 256 × 9 (CY7C4201)
— 512 × 9 (CY7C4211)
— 1K × 9 (CY7C4221)
— 2K × 9 (CY7C4231)
— 4K × 9 (CY7C4241)
— 8K × 9 (CY7C4251)
time)
operation
Almost Full status flags
IDT72421, 72201, 72211, 72221, 72231, and 72241
RS
WCLK
CONTROL
POINTER
WEN1
RESET
Write
Write
LOGIC
CC
WEN2/LD
= 35 mA)
OUTPUT REGISTER
64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
THREE-ST ATE
RAM Array
REGISTER
Dual Port
64 x 9
8k x 9
D 0 - 8
INPUT
Q 0 - 8
OE
RCLK
3901 North First Street
PROGRAM
REGISTER
CONTROL
POINTER
LOGIC
FLAG
Read
Read
FLAG
REN1 REN2
EF
PAE
PAF
FF
Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories
with clocked Read and Write interfaces. All are 9 bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
Write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running Read clock (RCLK) and two
Read-enable pins (REN1, REN2). In addition, the CY7C42X1
has an output enable pin (OE). The Read (RCLK) and Write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
Read/Write applications. Clock frequencies up to 100 MHz are
achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic
to direct the flow of data.
• Pb-Free Packages Available
Pin Configurations
CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
REN1
RCLK
REN2
GND
PAE
PAF
D
D
1
0
REN1
RCLK
REN2
GND
PAE
PAF
OE
D
D
1
0
1
2
3
4
5
6
7
8
San Jose
32
9 10 11 12 13
5
6
7
8
9
10
11
12
13
CY7C4421/4201/4211/4221
141516 171819 20
4 3 2 1
31 30
29 28 27
,
32
CA 95134
14 15 16
CY7C4231/4241/4251
3130
26
29
28
27
26
25
24
23
22
21
25
24
23
22
21
20
19
18
17
RS
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
CC
8
7
6
5
Revised August 2, 2005
WEN1
WCLK
WEN2/LD
V
Q
Q
Q
Q
Top View
Top View
CC
8
7
6
5
TQFP
PLCC
408-943-2600
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Related parts for CY7C4231-15AC

CY7C4231-15AC Summary of contents

Page 1

... LOGIC THREE-ST ATE OUTPUT REGISTER Cypress Semiconductor Corporation Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 CY7C4231/4241/425164/256/512/1K/2K/4K/ Synchronous FIFOs CY7C4421/4201/4211/4221 • Pb-Free Packages Available Functional Description The CY7C42X1 are high-speed, low-power FIFO memories with clocked Read and Write interfaces. All are 9 bits wide. The CY7C42X1 are pin-compatible to IDT722X1. Programmable features include Almost Full/Almost Empty flags ...

Page 2

... Resets device to empty condition. A reset is required before an initial Read or Write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High-Z (high-impedance) state. CY7C4421/4201/4211/4221 CY7C4231/4241/4251 -25 Unit 40 MHz ICC1 40 CY7C4231 CY7C4241 CY7C4251 2K × × × 9 Page [+] Feedback ...

Page 3

... The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK Read register contents to the data outputs. Writes and reads should not be preformed simultaneously on the offset registers. CY7C4231/4241/4251 outputs 0–8 Page [+] Feedback ...

Page 4

... Default Value = 007h × Empty Offset (LSB) Reg. Default Value = 007h (MSB) 0000 Full Offset (LSB) Reg Default Value = 007h (MSB) 0000 CY7C4231/4241/4251 1K × Empty Offset (LSB) Reg. Default Value = 007h (MSB) (MSB Full Offset (LSB) Reg Default Value = 007h (MSB) ...

Page 5

... Full Offset ( default value). Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 (256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m), CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m. Table 1. Writing the Offset Registers ...

Page 6

... REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. RESET (RS) 9 CY7C42X1 Read Enable 2 (REN2) Used in a Width Expansion Configuration CY7C4421/4201/4211/4221 CY7C4231/4241/4251 Read CLOCK (RCLK) Read ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF EMPTY FLAG (EF) #2 DATA OUT ( Page ...

Page 7

... Max. –10 +10 = Max., –90 = GND , –10 +10 IH < V < Commercial 35 Industrial 40 Commercial 10 Industrial 15 Test Conditions ° MHz 5.0V CC CY7C4421/4201/4211/4221 CY7C4231/4241/4251 Ambient Temperature V CC ° ° + ±10% ° ° – + ±10% -15 -25 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 V 2.2 ...

Page 8

... Values guaranteed by design, not currently tested. Document #: 38-06016 Rev. *C [11, 12] 3.0V R2 GND 680Ω ≤ THÉ VENIN EQUIVALENT 420Ω OUTPUT -10 Min. Max. 100 4.5 4.5 3 0 [14 [14 CY7C4421/4201/4211/4221 CY7C4231/4241/4251 ALL INPUT PULSES 90% 90% 10% 10% ≤ 1.91V -15 -25 Min. Max. Min. Max. Unit 66.7 40 MHz ...

Page 9

... CLKL NO OPERATION t REF VALID DATA t OE [16] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW1 CY7C4421/4201/4211/4221 CY7C4231/4241/4251 NO OPERATION NO OPERATION t WFF REF t OHZ Page [+] Feedback ...

Page 10

... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06016 Rev RSR RSS t t RSS RSR t t RSR RSS t RSF t RSF t RSF D D VALID Write [20] t FRL t SKEW1 t REF [21 OLZ When t < minimum specification, t CLK SKEW1 SKEW1 CY7C4421/4201/4211/4221 CY7C4231/4241/4251 [19 (maximum) = either 2 FRL CLK SKEW1 Page [+] Feedback ...

Page 11

... ENH ENS WEN1 WEN2 (if applicable ENS ENH [20] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 t DS DATAWRITE2 t ENS t t ENS ENH REF REF SKEW1 t A CY7C4231/4241/4251 t ENH [20] t FRL t REF DATA Read Page [+] Feedback ...

Page 12

... DATA Write t WFF DATA Read t CLKL t ENS ENH t Note ENS ENH 23 [22] t PAE t ENS , then PAE may not change state until the next RCLK. CY7C4421/4201/4211/4221 CY7C4231/4241/4251 NO Write [15] DATA Write t WFF t ENH t ENS t A NEXT DATA Read WORDS Note INFIFO t PAE ENS ...

Page 13

... If a Write is performed on this rising edge of the Write clock, there will be Full – (m – 1) words of the FIFO when PAF goes LOW. 26. PAF offset = m. 27. 64-m words for CY7C4421, 256 – m words in FIFO for CY7C4201, 512 – m words for CY7C4211, 1024 – m words for CY7C4221, 2048 – m words for CY7C4231, 4096 – m words for CY7C4241, 8192 – m words for CY7C4251. ...

Page 14

... Switching Waveforms (continued) Read Programmable Registers t CLK t CLKH RCLK t ENS WEN2/LD t ENS REN1, REN2 Q – Document #: 38-06016 Rev. *C CY7C4421/4201/4211/4221 t CLKL t ENH t A UNKNOWN PAE OFFSET LSB PAE OFFSET MSB CY7C4231/4241/4251 PAF OFFSET MSB PAF OFFSET LSB Page [+] Feedback ...

Page 15

... V = 5.0V CC 1.25 1.00 0.75 0.50 −55 25 125 AMBIENT TEMPERATURE (°C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 160 140 120 100 OUTPUT VOLTAGE (V) CY7C4231/4241/4251 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1. 5. 25°C 1. 3.0V IN 0.90 0.80 0.70 0. 100 FREQUENCY (MHz) TYPICAL t CHANGE vs. A OUTPUT LOADING 40 25 ...

Page 16

... A32 32-lead Pb-Free Thin Quad Flatpack J65 32-lead Plastic Leaded Chip Carrier J65 32-lead Pb-Free Plastic Leaded Chip Carrier A32 32-lead Thin Quad Flatpack J65 32-lead Plastic Leaded Chip Carrier CY7C4231/4241/4251 Operating Range Commercial Commercial Operating Range Commercial Commercial Commercial Industrial ...

Page 17

... Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4231-10AC CY7C4231-10JC 15 CY7C4231-15AC CY7C4231-15AXC CY7C4231-15JC CY7C4231-15JXC 25 CY7C4231-25AC CY7C4231-25JC Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4241-10AC CY7C4241-10AXC CY7C4241-10JC CY7C4241-10JI 15 CY7C4241-15AC CY7C4241-15AXC CY7C4241-15JC CY7C4241-15JXC 25 CY7C4241-25AC CY7C4241-25JC CY7C4241-25JI Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4251-10AC CY7C4251-10JC CY7C4251-10JXC CY7C4251-10AI CY7C4251-10AXI 15 CY7C4251-15AC CY7C4251-15AXC ...

Page 18

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 32-Lead Plastic Leaded Chip Carrier J65 CY7C4421/4201/4211/4221 CY7C4231/4241/4251 51-85063-*B 51-85002-*B Page ...

Page 19

... Document Title: CY7C4421/4201/4211/4221, CY7C4231/4241/4251 64/256/512/1K/2K/4K/ Synchronous FIFOs Document Number: 38-06016 Issue Orig. of REV. ECN NO. Date Change ** 106477 09/10/01 *A 110725 03/20/02 *B 122268 12/26/02 *C 386306 See ECN Document #: 38-06016 Rev. *C Description of Change SZV Change from Spec number: 38-00419 to 38-06016 FSG Change Input Leakage current I ...

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