S25FL016A0LMFI011 Spansion Inc., S25FL016A0LMFI011 Datasheet - Page 19

• Manufacturer Part Number: S25FL016A0LMFI011
• Manufacturer: Spansion Inc.

Specifications of S25FL016A0LMFI011

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 10ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Compliant

9.5
9.6
February 27, 2009 S25FL016A_00_C4
Write Disable (WRDI)
Read Status Register (RDSR)
The Write Disable (WRDI) command (see
disables the device from accepting a Write Status Register, program, or erase command. The host system
must first drive CS# low, write the WRDI command, and then drive CS# high.
Any of following conditions resets the WEL bit:
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
the status register bits and their functions.
The RDSR command may be written at any time, even while a program, erase, or Write Status Register
operation is in progress. The host system should check the Write In Progress (WIP) bit before sending a new
command to the device if an operation is already in progress.
sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven
high.
Power-up
Write Disable (WRDI) command completion
Write Status Register (WRSR) command completion
Page Program (PP) command completion
Sector Erase (SE) command completion
Bulk Erase (BE) command completion
Bit
7
6
5
4
3
2
1
0
Status Register Bit
SRWD
WEL
BP2
BP1
BP0
WIP
—
—
D a t a
Figure 9.5 Write Disable (WRDI) Command Sequence
SCK
CS#
SO
SI
Status Register Write Disable
Mode 3
Mode 0
Hi-Z
Write Enable Latch
Write in Progress
Table 9.2 S25FL016A Status Register
S h e e t
Bit Function
Block Protect
S25FL016A
—
—
Figure
0 1 2 3 4 5 6 7
9.5) resets the Write Enable Latch (WEL) bit to a 0, which
Command
1 = Protects when W# is low
0 = No protection, even when W# is low
Not used
Not used
000–111 = Protects upper half of address range in 5 sizes. See
Table 7.1 on page
1 = Device accepts Write Status Register, program, or erase
commands
0 = Ignores Write Status Register, program, or erase commands
1 = Device Busy. A Write Status Register, program, or erase
operation is in progress
0 = Ready. Device is in standby mode and can accept commands.
Figure 9.6
13.
shows the RDSR command
Description
Table 9.2
shows
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