SLATA5GM1U STEC, SLATA5GM1U Datasheet - Page 25

• Manufacturer Part Number: SLATA5GM1U
• Manufacturer: STEC

Specifications of SLATA5GM1U

• Lead Free Status / RoHS Status: Compliant

SLATAxxx(M/G)M1U(I)
Datasheet
C3 41 99 01 55 EA 61 70 01 07 76 03 01 EE 20
Configuration Table Index is 03 (default)
Interface type is I/O
BVDs not active, WP not active, RdyBsy active
Wait signal support not required
Vcc Power Description:
Nom V = 5.0 V
Decode 10 I/O lines, bus size 8 or 16
I/O block at 0170, length 8
I/O block at 0376, length 2
IRQ may be shared, pulse and level mode interrupts
are supported
Only IRQ14 is supported
Miscellaneous Features:
Max Twins 0, -Audio, -ReadOnly, +PowerDown
Tuple CISTPL_CFTABLE_ENTRY (1B), length 15
007D: Code 1B, link 0F
(0F) at offset 7D
61000-04497-104, January 2007
03 01 21 B5 1E 4D
Configuration Table Index is 03
Vcc Power Description:
Nom V = 3.30 V
Peak I = 45.0 mA
Tuple CISTPL_CFTABLE_ENTRY (1B), length 6
Tuple CISTPL_NO_LINK (14), length 0 (00) at
Tuple CISTPL_END (FF) at offset 98
008E: Code 1B, link 06
0096: Code 14, link 00
(06) at offset 8E
0098: Code FF
offset 96
ATA PC Card
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