MPC2605ZP83 Freescale, MPC2605ZP83 Datasheet - Page 6

• Manufacturer Part Number: MPC2605ZP83
• Manufacturer: Freescale

Specifications of MPC2605ZP83

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Not Compliant

MPC2605/D
PIN DESCRIPTIONS (continued)
6
*See Pin Assignment for specific pin assignment of these bus signals.
8H – 10H, 4J, 8J, 9J, 16J,
4K, 8K, 12K, 16K, 4L, 11L,
7C, 9C, 13C, 14C, 7D, 8D,
12D, 13D, 4G, 16G – 18G,
16M, 4N, 16N, 7T, 8T, 12T,
13T, 5U – 7U, 12U – 14U
12L, 16L, 10M – 12M, 3T,
4C, 15C, 16C, 9D – 11D,
8L – 10L, 4M, 8M, 9M,
9T – 11T, 17T, 3U, 4U,
10J – 12J, 9K – 11K,
1K, 2K, 1L, 2L, 1M *
4H, 11H, 12H, 16H,
Pin Locations
17F – 19F *
15U, 17U
3F, 3R
3B
2N
3N
1N
1E
3K
2P
1P
1R
1H
3P
2R
3H
3J
3L
L2 UPDATE INH
TSIZ0 – TSIZ2
L2 MISS INH
L2 TAG CLR
Integrated Secondary Cache for Microprocessors
Pin Name
TT0 – TT4
SRESET
PWRDN
Freescale Semiconductor, Inc.
TBST
TRST
TDO
TMS
TCK
TEA
V
V
TDI
WT
NC
TS
TA
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Go to: www.freescale.com
Supply Power supply: 3.3 V ± 5%.
Supply Ground.
Type
I/O
I/O
I/O
I/O
I/O
I/O
—
O
I
I
I
I
I
I
I
I
I
I
Prevents line fills on misses when asserted.
Invalidates all tags and holds cache in a reset condition.
Cache disable. When asserted, the MPC2605 will not respond to
signals on the local bus and internal states do not change.
Provides low power mode. Prevents address and data transitions
into the RAM array. MPC2605 becomes active 4 s after
deassertion. Clock must be externally disabled.
Soft reset signal from processor bus. This is an asynchronous signal
that takes 8 to 16 clock cycles to synchronize. When asserted, this
resets the internal data state machine.
Transfer acknowledge status I/O from processor bus.
Transfer burst status I/O from processor bus. Used to distinguish
between burstable and non-burstable memory operations.
Test clock input for IEEE 1149.1 boundary scan (JTAG).
Test data input for IEEE 1149.1 boundary scan (JTAG).
Test data output for IEEE 1149.1 boundary scan (JTAG).
Transfer error acknowledge status input from processor bus.
Test mode select for IEEE 1149.1 boundary scan (JTAG).
Test reset input for IEEE 1149.1 boundary scan (JTAG). If JTAG will
not be used, TRST should be tied low.
Transfer start I/O from processor bus (can also come from any bus
master on the processor bus). Signals the start of either a processor
or bus master cycle.
Transfer size I/O from processor bus.
Transfer type I/O from processor bus.
Write through status input from processor bus. When tied to ground,
the MPC2605 will operate in write-through mode only (no copy
back).
No connection. There is no connection to the chip.
Description
MOTOROLA