EV2A08AVNYU35 E2V, EV2A08AVNYU35 Datasheet - Page 10
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EV2A08AVNYU35
Manufacturer Part Number
EV2A08AVNYU35
Description
Manufacturer
E2V
Datasheet
1.EV2A08AVNYU35.pdf
(13 pages)
Specifications of EV2A08AVNYU35
Lead Free Status / RoHS Status
Supplier Unconfirmed
Figure 2-7.
10
W (Write Enable)
1024B–HIREL–10/10
EV2A08A
E (Chip Enable)
Q (Data Out)
A (Address)
D (Data In)
Write Cycle Timing 2 (E Controlled)
Table 2-9.
Notes:
Parameter
Write cycle time
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Enable to end of write (G high)
Enable to end of write (G low)
Data valid to end of write
Data hold time
Write recovery time
1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and
2. All write cycle timings are referenced from the last valid address to the first transition address.
3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If
decoupled and bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high impedance state.
After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
E goes high at the same time or before W goes high, the output will remain in a high-impedance state.
Write Cycle Timing 2 (E Controlled)
(2)
(3)
t
AVEL
t
t
AVAV
AVEH
Hi-Z
Symbol
t
t
t
t
t
t
t
t
t
t
t
ELWH
ELWH
DVEH
EHDX
EHAX
AVEH
AVEH
ELEH
ELEH
AVAV
AVEL
(1)
t
ELEH
t
ELWH
Min
35
18
20
15
15
10
12
0
0
Data Valid
t
DVEH
Max
e2v semiconductors SAS 2010
–
–
–
–
–
–
–
–
–
t
EHDX
t
EHAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns