CY7C1470V25-250BZC Cypress Semiconductor Corp, CY7C1470V25-250BZC Datasheet
CY7C1470V25-250BZC
Specifications of CY7C1470V25-250BZC
Related parts for CY7C1470V25-250BZC
CY7C1470V25-250BZC Summary of contents
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... FBGA package • IEEE 1149.1 JTAG Boundary Scan compatible • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Logic Block Diagram-CY7C1470V25 (2M x 36) A0, A1, A REGISTER 0 MODE CLK ...
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... REGISTER A0' BURST D0 Q0 LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY MEMORY AND DATA COHERENCY WRITE ARRAY CONTROL LOGIC DRIVERS INPUT REGISTER 1 READ LOGIC Sleep Control 250 MHz 200 MHz 3.0 3.0 450 450 120 120 CY7C1470V25 CY7C1472V25 CY7C1474V25 DQs DQP T ...
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... DQb DQa 18 63 DQa DQb DDQ 20 61 DDQ DQa DQb 22 59 DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1470V25 CY7C1472V25 CY7C1474V25 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa DQa 63 DQa DDQ DQa 59 DQa ...
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... DQ V DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE NC/576M NC/1G A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC/144M MODE A Document #: 38-05290 Rev. *I CY7C1470V25 ( CEN CLK TDI A1 TDO A A0 TCK A TMS CY7C1472V25 ( CEN CLK ...
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... DDQ MODE TDI Pin Description controls DQ a and DQP , BW controls DQ and DQP and DQP BW controls DQ and DQP CY7C1470V25 CY7C1472V25 CY7C1474V25 DQb DQb 3 BWS DQb DQb b f BWS DQb DQb DQb DQb DQPf DQPb DDQ DDQ V DQf V DQf DQf DQf DDQ DDQ ...
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... The direction of the pins is [18:0] –DQ are placed in a tri-state condition. The outputs are automat controlled DQP is controlled controlled DQP is controlled DQP is controlled CY7C1470V25 CY7C1472V25 CY7C1474V25 . During [71:0] , DQP is controlled DQP is controlled Page [+] Feedback ...
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... The correct BW (BW CY7C1470V25 CY7C1472V25 CY7C1474V25 , CE 1 for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 and DQ /DQP a,b a,b for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 & DQ /DQP a,b a,b for CY7C1474V25, BW a,b,c,d for CY7C1472V25) signals. The a,b /DQP for CY7C1474V25, a,b,c,d,e,f,g,h for CY7C1470V25 and DQ /DQP a,b ...
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... CY7C1474V25, BW for CY7C1470V25 and BW a,b,c,d CY7C1472V25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” ...
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... Partial Write Cycle Description Function (CY7C1470V25) Read Write – No bytes written Write Byte a – (DQ and DQP ) a a Write Byte b – (DQ and DQP ) b b Write Bytes b, a Write Byte c – (DQ and DQP ) c c Write Bytes c, a Write Bytes c, b Write Bytes Write Byte d – (DQ ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1470V25/CY7C1472V25/CY7C1474V25 incorpo- rates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
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... TAP controller’s capture set-up plus hold time (t plus portion of The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue still CY7C1470V25 CY7C1472V25 CY7C1474V25 Unlike the SAMPLE/PRELOAD Page [+] Feedback ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [9, 10] Over the Operating Range Description / ns CY7C1470V25 CY7C1472V25 CY7C1474V25 TDOV Min. Max. Unit MHz ...
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... I DDQ CY7C1472V25 CY7C1474V25 (2M x 36) (4M x 18) (1M x 72) 000 000 000 01011 01011 01011 001000 001000 001000 100100 010100 110100 00000110100 00000110100 1 1 CY7C1470V25 CY7C1472V25 CY7C1474V25 – 0.2 DDQ 0.9V 50Ω 50Ω 20pF O Min. Max. Unit 1.7 V 2.1 V 1.6 V 0.4 V 0 ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM opera- tions. Document #: 38-05290 Rev. *I Bit Size (x36) Bit Size (x18 – – Description CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit Size (x72 – 110 Page [+] Feedback ...
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... L10 59 B8 K11 60 A7 165-Ball ID Bit # 165-Ball L10 P6 28 K10 R6 29 J10 R8 30 H11 P3 31 G11 P4 32 F11 P8 33 E11 P9 34 D11 P10 35 C11 R9 36 A11 R10 37 A9 R11 38 B9 M10 39 A10 CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit # 165-Ball Bit # 165-Ball ID 40 B10 ...
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... J11 V5 72 J10 U5 73 H11 U6 74 H10 W7 75 G11 V7 76 G10 U7 77 F11 V8 78 F10 V9 79 E10 W11 80 E11 W10 81 D11 V11 82 D10 V10 83 C11 U11 84 C10 CY7C1470V25 CY7C1472V25 CY7C1474V25 Bit # 209-Ball ID 85 B11 86 B10 87 A11 88 A10 100 B3 101 C3 102 C4 103 ...
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... All speed grades DD ≥ V ≤ /2), undershoot: V (AC)> –2V (Pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1470V25 CY7C1472V25 CY7C1474V25 Ambient Temperature DDQ 0°C to +70°C 2.5V –5%/+5% 1. Min. Max. 2.375 2.625 2.375 V DD 1.7 1.9 2.0 1 ...
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... EIA/JESD51 1667Ω 2.5V V DDQ OUTPUT GND 1538Ω INCLUDING JIG AND (b) SCOPE KΩ 1.8V V DDQ OUTPUT 0 KΩ INCLUDING JIG AND (b) SCOPE CY7C1470V25 CY7C1472V25 CY7C1474V25 100 TQFP 165 FBGA 209 FBGA Max. Max. Max. Unit ...
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... V minimum initially, before a Read or Write operation can be DD and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1470V25 CY7C1472V25 CY7C1474V25 –200 –167 Min. Max. Min. Max. ...
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... DOH CLZ D(A1) D(A2) D(A2+1) Q(A3) t BURST READ READ BURST WRITE Q(A3) Q(A4) READ D(A2+1) Q(A4+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1470V25 CY7C1472V25 CY7C1474V25 OEV CHZ Q(A4) Q(A4+1) D(A5) Q(A6) OEHZ t DOH t OELZ WRITE READ WRITE ...
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... Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 26. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05290 Rev D(A1) Q(A2) Q(A3) READ WRITE STALL Q(A3) D(A4) DON’T CARE High-Z DON’T CARE CY7C1470V25 CY7C1472V25 CY7C1474V25 CHZ D(A4) Q(A5) NOP READ DESELECT CONTINUE Q(A5) DESELECT UNDEFINED t ZZREC ...
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... CY7C1470V25-167AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1472V25-167AXC CY7C1470V25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) CY7C1472V25-167BZC CY7C1470V25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4mm) Lead-Free CY7C1472V25-167BZXC CY7C1474V25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) CY7C1474V25-167BGXC CY7C1470V25-167AXI 51-85050 100-Pin Thin Quad Flat Pack ( ...
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... Ordering Code Diagram 250 CY7C1470V25-250AXC 51-85050 100-Pin Thin Quad Flat Pack ( 1.4 mm) Lead-Free CY7C1472V25-250AXC CY7C1470V25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1472V25-250BZC CY7C1470V25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Lead-Free CY7C1472V25-250BZXC CY7C1474V25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) ...
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... JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1470V25 CY7C1472V25 CY7C1474V25 1.40±0.05 12°±1° A ...
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... Package Diagrams (continued) 165-Ball FBGA ( 1.4 mm) (51-85165) TOP VIEW PIN 1 CORNER SEATING PLANE C Document #: 38-05290 Rev 0.15(4X) CY7C1470V25 CY7C1472V25 CY7C1474V25 PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X 1.00 5.00 10.00 B 15.00±0.10 51-85165-*A Page [+] Feedback ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1470V25 CY7C1472V25 ...
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... Document History Page Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 Orig. of REV. ECN No. Issue Date Change ** 114677 08/06/02 PKS *A 121519 01/27/03 CJM *B 223721 See ECN NJY *C 235012 See ECN RYQ *D 243572 See ECN ...
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... Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05290 *I 472335 See ECN VKN Document #: 38-05290 Rev. *I Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for from V SS Added the Maximum Rating for Supply Voltage on V ...