CY7C1470V25-250BZC Cypress Semiconductor Corp, CY7C1470V25-250BZC Datasheet - Page 8

• Manufacturer Part Number: CY7C1470V25-250BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1470V25-250BZC

• Density: 72Mb
• Access Time (max): 3ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 250MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 21b
• Package Type: FBGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 450mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 165
• Word Size: 36b
• Number Of Words: 2M
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-05290 Rev. *I
CY7C1474V25, BW
CY7C1472V25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
ZZ Mode Electrical Characteristics
Truth Table
I
t
t
t
t
Deselect Cycle
Continue Deselect Cycle
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW
2. Write is defined by WE and BW
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles.During a Read cycle DQ
signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
OE is inactive or when the device is deselected, and DQ
Parameter
Operation
[1, 2, 3, 4, 5, 6, 7]
ZZREC
a,b,c,d
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
1
, CE
after the ZZ input returns LOW.
for CY7C1470V25 and BW
2
[a:d]
, and CE
. See Write Cycle Description table for details.
Description
3
Address
External
External
External
, must remain inactive
Current
Used
None
None
None
None
Next
Next
Next
Next
s
= data when OE is active.
CE
H
X
L
X
L
X
L
X
L
X
X
X
a,b
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
for
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ADV/LD WE BW
Linear Burst Address Table (MODE = GND)
Interleaved Burst Address Table
(MODE = Floating or V
DD
H
H
H
H
H
DD
L
L
L
L
X
X
L
− 0.2V
Address
Test Conditions
− 0.2V
Address
A1,A0
A1,A0
First
First
00
01
10
11
00
01
10
11
X
X
H
X
H
X
X
X
X
X
L
L
x
= L signifies at least one Byte Write Select is active, BW
H
H
X
X
X
X
X
X
X
X
L
L
x
Address
Second
Address
OE
Second
A1,A0
X
X
H
H
X
X
X
X
X
X
L
L
A1,A0
01
00
11
10
01
10
00
11
CEN
H
X
L
L
L
L
L
L
L
L
L
L
DD
)
2t
Min.
CLK
CYC
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Address
Address
0
s
X
A1,A0
A1,A0
and DQP
CY7C1470V25
CY7C1472V25
CY7C1474V25
Third
Third
10
00
01
10
00
01
11
11
2t
2t
[a:d]
Max.
Data Out (Q)
Data Out (Q)
120
Data In (D)
Data In (D)
CYC
CYC
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
= Tri-state when
Page 8 of 28
DQ
Address
Address
–
Fourth
Fourth
A1,A0
A1,A0
11
10
01
00
11
00
01
10
x
Unit
mA
= Valid
ns
ns
ns
ns
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