MCIMX27VJP4A Freescale, MCIMX27VJP4A Datasheet - Page 94
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MCIMX27VJP4A
Manufacturer Part Number
MCIMX27VJP4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX27VJP4A.pdf
(152 pages)
Specifications of MCIMX27VJP4A
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Electrical Characteristics
94
1
Note:
WE11
WE26
WE27
WE10
WE12
WE13
WE14
WE15
WE15
WE16
WE17
WE18
WE19
WE20
WE21
WE22
WE23
WE24
WE25
WE5
WE6
WE7
WE8
WE9
BCLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal
value and low is defined as 50% of signal value.
ID
High is defined as 80% of signal value and low is defined as 20% of signal
value.
Clock rise/fall to RW Valid
Clock rise/fall to RW Invalid
Clock rise/fall to OE Valid
Clock rise/fall to OE Invalid
Clock rise/fall to EB[x] Valid
Clock rise/fall to EB[x] Invalid
Clock rise/fall to LBA Valid
Clock rise/fall to LBA Invalid
Clock rise/fall to Output Data Valid
Clock rise to Output Data Invalid
Input Data Valid to Clock rise, FCE=0 (in the case there is
ECB_B asserted during access)
Input Data Valid to Clock rise, FCE=0 (in the case there is NO
ECB_B asserted during access)
Cloc/k rise to Input Data Invalid, FCE=0
Input Data Valid to Clock rise, FCE=1
Clock rise to Input Data Invalid, FCE=1
ECB setup time, FCE=0
ECB hold time, FCE=0
ECB setup time, FCE=1
ECB hold time, FCE=1
DTACK setup time
DTACK hold time
BCLK High Level Width
BCLK Low Level Width
BCLK Cycle time
Table 50. WEIM Bus Timing Parameters (continued)
1
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
1
1
Parameter
NOTE
1/2BCLK
0.90
0.90
1.17
1.17
0.73
0.73
1.03
1.03
1.04
1.04
+3.6
6.95
2.35
1.24
0.23
7.23
2.93
1.08
5.35
3.19
Min
3.0
3.0
7.5
0
1.8 V
Max
2.60
2.60
3.57
3.57
2.43
2.43
2.84
2.84
4.01
4.01
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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