mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet
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mcimx27- Summary of contents
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... Data Sheet Multimedia Applications Processor 1 Introduction The i.MX27 and i.MX27L (MCIMX27/MX27L) Multimedia Applications Processors represents the next step in low-power, high-performance application processors. Unless otherwise specified, the material in this data sheet is applicable to both the i.MX27 and i.MX27L processors and referred to singularly throughout this document as i ...
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Introduction • Portable DVD players • Digital cameras The i.MX27/MX27L processor features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 400 MHz, and is optimized for minimal power consumption using the most advanced techniques for power saving ...
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DDR/ SDRAM PCMCIA/CF SAHARA2 Bluetooth Note: The i.MX27L does not support the following: • ATA-6 HDD Interface • Memory Stick Pro • VPU: MPEG-4/.263/H.264 HW encoder/decoder • eMMA (PrP processing, CSC, deblock, dering) Figure 1. i.MX27/MX27L Simplified Interface Block Diagram ...
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... Ordering Information Table 1 provides ordering information for the MAPBGA, lead-free packages. MCIMX27VOP4A MCIMX27LVOP4A MCIMX27MOP4A MCIMX27LMOP4A 2 Functional Description and Application Information 2.1 ARM926 Microprocessor Core Platform The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9 × 3 Multi-Layer AHB crossbar switch (MAX), and a “primary AHB” complex. ...
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The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports of the MAX, are designed to support connections to multiple AHB masters external to the platform. An external arbitration AHB control module is ...
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Functional Description and Application Information Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name CRM Clock and Reset Module CSI CMOS Sensor Interface CSPI Configurable Serial Peripheral Interface (x3) DMAC Direct Memory Access Controller eMMA_lt eMMA_lt EMI External ...
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Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name IIM IC Identification Module JTAGC JTAG Controller KPP Keypad Port LCDC Liquid Crystal Display Controller M3IF Multi-Master Memory Interface MAX Multi-layer AHB Crossbar Switch MSHC Memory Stick Host Controller ...
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Functional Description and Application Information Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name RTC Real Time Clock RTIC Run-Time Integrity Checkers SAHARA2 Symmetric/ Asymmetric Hashing and Random Accelerator SCC Security Controller Module SDHC Secured Digital Host Controller ...
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Table 2. Digital and Analog Modules (continued) Block Mnemonic Block Name USB Universal Serial Bus–2 Host Controllers and 1 OTG (On-The-Go) Video Codec Video Codec WDOG Watchdog Timer Module WEIM Wireless External Interface Module 2.3 Module Descriptions This section provides ...
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Functional Description and Application Information 2.3.2 AHB-Lite IP Interface Module (AIPI) The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and lower bandwidth peripherals conforming to the IP bus specification Rev 2.0. There are two ...
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The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both instruction and data caches will be 16 kbytes on the platform. The cache is virtually accessed and virtually tagged. The data cached has physical tags as ...
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Functional Description and Application Information Included in the AUDMUX are two types of interfaces. The internal ports connect to the processor serial interfaces, and the external ports connect to off-chip audio devices and serial interfaces of other processors. A desired ...
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Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the camera (for Bayer data only) 2.3.9 Configurable Serial Peripheral Interface (CSPI) The Configurable Serial Peripheral Interface (CSPI) is used for fast data communication with ...
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Functional Description and Application Information Each module has individual control and configuration registers that are accessed via the IP interface, and are capable of bus mastering the AMBA bus to independently access system memory without any CPU intervention. This enables ...
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Output format: – YUV 4:2:2 (YUYV) – RGB16 and RGB32 bpp — Image Resize – Upscaling ratios ranging from 1:1 to 1:4 in fractional steps – Downscaling ratios ranging from 1:1 to 2:1 in fractional steps and a fixed ...
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Functional Description and Application Information — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode • Independent DMA engine with multiple channels allowing transmit data, transmit descriptor, receive data, ...
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The I C operates up to 400 kbps dependent on pad loading and timing. (For pad requirement details, refer 2 to Phillips I C Bus Specification, Version 2.1.) The I arbitration and collision detection that prevents data corruption if ...
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Functional Description and Application Information — Passive color panel: – 4 (mapped to RGB444 (mapped to RGB444 (RGB444) bits per pixel (bpp) — TFT panel: – 4 (mapped to RGB666 (mapped to RGB666) / ...
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Once the CRM is granted a port, no other master will receive a grant on that port until the CRM bus request (ccm_br) negates. 2.3.23 Memory Stick Host Controller (MSHC) The Memory Stick Host Controller (MSHC) is ...
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Functional Description and Application Information The pcmcia_if host adapter module provides the control logic for PCMCIA socket interfaces, and requires some additional external analog power switching logic and buffering. The additional external buffers allow the pcmcia_if host adapter module to ...
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If the memory contents at runtime fail to match the hash signature, an error in the security monitor is triggered. Contact your Freescale Semiconductor sales office or distributor for additional information on SCC, RTIC, IIM, SAHARA2 2.3.30 Symmetric/Asymmetric ...
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Functional Description and Application Information provides the capability for a higher memory capacity. The I/O card provides high-speed data I/O with low-power consumption for mobile electronic devices. 2.3.33 Smart Liquid Crystal Display Controller Module (SLCDC) The Smart Liquid Crystal Display ...
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I2S modes (Master, Slave, or Normal). Oversampling clock, ccm_ssi_clk is available as output from SRCK in I2S Master mode. In addition to AC97 support, the SSI has completely separate clock and frame sync selections for the receive and transmit ...
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Functional Description and Application Information • High Speed /Full Speed/Low Speed Host Only core (Host 2) • Full Speed/Low Speed interface for Serial transceiver • TLL function for direct connection to USB peripheral in FS/LS (serial) operation • High-speed OTG ...
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Watchdog Control Register (WCR) when there is a detection of a clock monitor event, an external reset, an external JTAG reset signal power-on-reset has occurred. 2.3.38 Wireless External Interface Module (WEIM) The Wireless External Interface Module ...
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Signal Descriptions – Quarter-pel and half-pel accuracy motion estimation – [+/-16, +/-16] Search range – Unrestricted motion vector — All variable block sizes are supported (in case of encoding, 8 × × 8, and 4 × 4 block ...
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Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name A [25:14] Address bus signals, shared with WEIM and PCMCIA SDBA[1:0] SDRAM/MDDR bank address signals SD[31:0] Data bus signals for SDRAM, MDDR SDQS[3:0] MDDR data sample strobe signals DQM0–DQM3 SDRAM data mask ...
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Signal Descriptions Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name PC_CD1_B PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20 PC_CD2_B PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19 PC_WAIT_B PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 ...
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Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name osc32K_bypass The signal for osc32k input bypass (Note: in the RTC power domain) BOOT [3:0] System Boot Mode Select—The operational system boot mode of the i.MX27/MX27L processor upon system reset is determined ...
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Signal Descriptions Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name UART1_CTS Clear to Send output signal; PE14 UART1_RXD Receive Data input signal; PE13 UART1_TXD Transmit Data output signal, PE12 UART2_RXD Receive Data input signal. This signal is multiplexed with KP_ROW6 ...
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Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name CSPI2_SS[2:0] Slave Select (Selectable polarity) signals, multiplexed with USBH2_DATA4/RXDM, USBH2_DATA3/RXDP, USBH2_DATA6/SPEED; PD19–PD21 CSPI2_SCLK Serial Clock signal, multiplexed with USBH2_DATA0/OEn; PD22 Note: CSPI3 CSPI3_MOSI, CSPI3_MISO, CSPI3_SS, andCSPI3_SCLK are multiplexed with SD1 signals. 2 ...
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Signal Descriptions Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name SSI3_CLK Serial clock signal which is output in master or input in slave. This signal is multiplexed with SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31. SSI3_TXD Transmit serial data signal ...
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Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name USBOTG_DATA0/Oen USB OTG data0/Output Enable signal; multiplexed with SLCDC1_DAT11 through PC9 USBOTG_DATA6/SPEED USB OTG data6/Suspend signal; multiplexed with SLCDC1_DAT10 and USBG_TXR_INT_B through PC8 USBOTG_DATA5/RCV USB OTG data5/RCV signal; multiplexed with SLCDC1_DAT9 through ...
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Signal Descriptions Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name Note: SLCDC signals are multiplexed with LCDC signals. ATA_DATA15–0 ATA Data Bus, [15:0] are multiplexed with ETMTRACEPKT4–12, FEC_MDIO, ETMTRACEPKT13–14 SD3_D3–0; Through GPIO also are multiplexed with SLCDC 15–0, and FEC ...
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Table 3. i.MX27/MX27L Signal Descriptions (continued) Pad Name Note: Both 1-Wire and Fast Ethernet Controller signals are multiplexed with other signals result these signal names do not appear in this list. The signals are listed below with the ...
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Signal Descriptions Pin Name Pad Type A0 regular A1 regular A2 regular A3 regular A4 regular A5 regular A6 regular A7 regular A8 regular A9 regular A10 regular MA10 regular A11 regular A12 regular A13 regular A14 regular A15 regular ...
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Pin Name Pad Type SD6 ddr SD7 ddr SD8 ddr SD9 ddr SD10 ddr SD11 ddr SD12 ddr SD13 ddr SD14 ddr SD15 ddr SD16 ddr SD17 ddr SD18 ddr SD19 ddr SD20 ddr SD21 ddr SD22 ddr SD23 ddr ...
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Signal Descriptions Pin Name Pad Type CS2 regular CS3 regular CS4 regular CS5 regular ECB regular LBA regular BCLK regular RW regular RAS regular CAS regular SDWE regular SDCKE0 regular SDCKE1 regular SDCLK regular SDCLK — SDQS0 ddr SDQS1 ddr ...
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Pin Name Pad Type D6 regular D5 regular D4 regular D3 regular D2 regular D1 regular D0 regular PC_CD1 regular PC_CD2 regular PC_WAIT regular PC_READY regular PC_PWRON regular PC_VS1 regular PC_VS2 regular PC_BVD1 regular PC_BVD2 regular PC_RST regular IOIS16 regular ...
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Signal Descriptions 3.3 Electrical Characteristics This section provides the chip-level and module-level electrical characteristics for the i.MX27/iMX27L: • Section 3.4, “i.MX27/iMX27L Chip-Level — Section 3.4.2, “Current — Section 3.4.3, “Test Conditions and Recommended • Section 3.5, “Module-Level Electrical — Section ...
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Table 5. i.MX27/iMX27L Chip-Level Conditions (continued) Table 10, “Frequency Definition for Power Consumption Measurement” Table 11, “Current Consumption” Section 3.4.3, “Test Conditions and Recommended Settings” Table 6 provides the DC absolute maximum operating conditions. Stresses beyond those listed under device. ...
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Signal Descriptions Table 7. DC Operating Conditions (continued) ID Parameter 9 Fusebox Program Supply Voltage 10 OSC32V DD 11 OSC26V DD 12 Operating Ambient Temperature (17mm x17mm package) 13 Operating Ambient Temperature (19mm x19mm package) 1 Segments 11, 14, 15 ...
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Table 10. Frequency Definition for Power Consumption Measurement (continued MCU AHB bus 4 MCU IP bus 5 OSC32 Table 11 shows the power consumption for the i.MX27/iMX27L device. ID Parameter 1 RUN Current RUN Current @266 MHz (QV ...
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Signal Descriptions 3.5 Module-Level Electrical Specifications This section contains the i.MX27/iMX27L electrical information including timing specifications, arranged in alphabetical order by module name. 3.5.1 Pads IO (PADIO) Electricals 3.5.1.1 DC Electrical Characteristics The over-operating characteristics appear in Rate) pads (unless ...
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Table 12. GPIO Pads DC Electrical Parameters (continued) Parameter Input current (22 kΩ PU) Input current (47 kΩ PU) Input current (100 kΩ PU) Input current (100 kΩ PD) Tri-state input leakage current High Level DC Input Voltage Low-Level DC ...
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Signal Descriptions 3.5.1.2 AC Electrical Characteristics Figure 2 depicts the load circuit for output pads. The range of operating conditions appear in and Table 16 for DDR I/O (unless otherwise noted). Output (at pad) Figure 3. Output Pad Transition Time ...
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Table 16. AC Electrical Characteristics of DDR I/O Pads ID Parameter PA1 Output Pad Transition Times (DDR Drive) Output Pad Transition Times (Max High) Output Pad Transition Times (High) Output Pad Transition Times (Normal) Maximum Input Transition Times 3.5.2 1-Wire ...
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Signal Descriptions Table 18. WR0 Sequence Timing Parameters ID Parameter OW5 Write 0 Low Time OW6 Transmission Time Slot Figure 6 depicts Write 1 Sequence timing, the timing parameters. One-Wire bus (BATT_LINE) One-Wire bus (BATT_LINE) ID Parameter OW7 Write 1/Read ...
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There are different requirements of timing relationships among the function pins conform with ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers. Below defines the AC characteristics of all the interface signals on all data transfer ...
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Signal Descriptions 3.5.5.1 Gated Clock Mode Timing VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is ...
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VSYNC HSYNC PIXCLK DATA[7:0] Figure 10. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Rising Edge, Table 21. Gated Clock Mode Timing Parameters Number 1 csi_vsync to csi_hsync 2 csi_hsync to csi_pixclk 3 csi_d setup time 4 csi_d hold time ...
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Signal Descriptions For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns. positive duty cycle = 10 max rise time allowed = 5 –1 ...
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VSYNC PIXCLK DATA[7:0] Figure 12. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Rising Edge, Table 22. Non-Gated Clock Mode Parameters Number csi_vsync to csi_pixclk csi_d setup time csi_d hold time csi_pixclk high time csi_pixclk low time csi_pixclk high time HCLK ...
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Signal Descriptions 3.6 Timing Diagrams Figure 13 and Figure 14 depict the master mode and slave mode timing diagrams of the CSPI and lists the timing parameters. The values shown in timing diagrams were tested using a worst case core ...
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ID Parameter Description Num t1 CSPI master SCLK cycle time t2 CSPI master SCLK high time t3 CSPI master SCLK low time t1’ CSPI slave SCLK cycle time t2’ CSPI slave SCLK high time t3’ CSPI slave SCLK low time ...
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Signal Descriptions 3.6.1 Direct Memory Access Controller (DMAC) After assertion of External DMA Request the DMA burst will start when the corresponding DMA channel becomes the current highest priority channel. The External DMA Request should be kept asserted until it ...
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Parameter Description T Minimum assertion time of External Grant signal min_assert T Maximum External Request assertion time after max_req_assert assertion of Grant signal T Maximum External Request assertion time after max_read first read completion T Maximum External Request assertion time ...
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Signal Descriptions Table 25. MII Receive Signal Timing Parameters (continued FEC_RX_CLK pulse width high M4 FEC_RX_CLK pulse width low 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. 3.6.2.2 MII Transmit Signal ...
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Table 27. MII Asynchronous Inputs Signal Timing Parameter FEC_CRS to FEC_COL minimum pulse width 1 FEC_COL has the same timing in 10 Mbit 7-wire interface mode. 3.6.2.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) The FEC ...
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Signal Descriptions 3.6.3 Inter IC Communication (I This section describes the electrical information of the I 2 3.6.3 Module Timing The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, ...
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Tck (input) J3 TCK (input) Data (inputs) Data (outputs) Data (outputs) Data (outputs) Freescale Semiconductor J2 Figure 22. Test Clock Input Timing Diagram J4 Input Data Valid J6 Output Data Valid J7 J6 Output Data Valid Figure 23. Boundary Scan ...
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Signal Descriptions TCK (input) TDI, TMS (inputs) TD0 (outputs) TD0 (outputs) TD0 (outputs) TCK (input) TRST (input TCK cycle time in crystal mode J2 TCK clock pulse width measured TCK rise and fall times J4 ...
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Table 30. JTAGC Timing Parameters (continued TCK low to output data valid J7 TCK low to output high impedance J8 TMS, TDI data set-up time J9 TMS, TDI data hold time J10 TCK low to TDO data valid ...
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Signal Descriptions Table 31. LCDC Non-TFT Mode Timing Parameters (continued setup time T4 LD hold time T5 Wait between LP and FLM rising edge T6 Wait between last data and LP rising edge pixel ...
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Memory Stick Host Controller (MSHC) Figure 30, Figure 28, and Figure 29 parameters. The i.MX27L does not contain an MSHC module. MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Input) Figure 28. Transfer Operation Timing Diagram (Serial) Freescale Semiconductor show the MSHC ...
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Signal Descriptions MSHC_SCLK MSHC_BS MSHC_DATA (Output) MSHC_DATA (Input) Figure 29. Transfer Operation Timing Diagram (Parallel) MSHC_SCLK tSCLKr Table 33. Serial Interface Timing Parameters Signal Parameter MSHC_SCLK Cycle H pulse length L pulse length Rise time Fall time 66 tSCLKc tBSsu ...
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Table 33. Serial Interface Timing Parameters (continued) Signal Parameter MSHC_BS Setup time Hold time MSHC_DATA Setup time Hold time Output delay time Table 34. Parallel Interface Timing Parameters Signal Parameter MSHC_SCLK Cycle H pulse length L pulse length Rise time ...
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Signal Descriptions NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 31. Command Latch Cycle Timing Diagram NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 32. Address Latch Cycle Timing Diagram 68 NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF9 NF8 command NF1 NF4 NF3 ...
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NFCLE NFCE NFWE NFALE NFIO[15:0] NFCLE NFCE NFRE NFRB NFIO[15:0] ID Parameter NF1 NFCLE Setup Time NF2 NFCLE Hold Time NF3 NFCE Setup Time NF4 NFCE Hold Time Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to ...
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Signal Descriptions Table 35. NFC Target Timing Parameters (continued) ID Parameter NF5 NF_WP Pulse Width NF6 NFALE Setup Time NF7 NFALE Hold Time NF8 Data Setup Time NF9 Data Hold Time NF10 Write Cycle Time NF11 NFWE Hold Time NF12 ...
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HCLK HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE Figure 35. Write Accesses Timing Diagram—PSHT=1, PSST=1 Freescale Semiconductor ADDR 1 CONTROL 1 DATA write 1 OKAY ADDR 1 DATA write 1 REG PSST i.MX27 and ...
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Signal Descriptions HCLK HADDR CONTROL RWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RD/WR POE Figure 36. Read Accesses Timing Diagram—PSHT=1, PSST=1 Table 36. PCMCIA Write and Read Timing Parameters Symbol PSHT PCMCIA strobe hold time PSST PCMCIA strobe ...
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SDCLK SDCLK CS SD4 RAS SD5 CAS SD4 WE SD6 ADDR ROW/BA DQ DQM Figure 37. SDRAM Read Cycle Timing Diagram Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters ID SD1 SDRAM clock high-level width SD2 SDRAM clock low-level width ...
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Signal Descriptions Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters (continued SD9 Data out hold time SD10 Active to read/write command period 1 Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related ...
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SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 38. SDR SDRAM Write Cycle Timing Diagram Table 38. SDR SDRAM Write Timing Parameters ID SD1 SDRAM clock high-level width SD2 SDRAM clock low-level width SD3 SDRAM ...
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Signal Descriptions Table 38. SDR SDRAM Write Timing Parameters (continued) ID SD13 Data setup time SD14 Data hold time 1 SD11 and SD12 are determined by SDRAM controller register settings. SDR SDRAM CLK parameters are being measured from the 50% ...
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Table 39. SDRAM Refresh Timing Parameters (continued) ID Parameter SD6 Address setup time SD7 Address hold time SD10 Precharge cycle period SD11 Auto precharge command period 1 SD10 and SD11 are determined by SDRAM controller register settings. SDR SDRAM CLK ...
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Signal Descriptions The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 40. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter SD16 CKE output delay time SDCLK SDCLK DQS (output) ...
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SDCLK SDCLK SD23 DQS (input) DQ (input) Figure 42. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram Table 42. Mobile DDR SDRAM Read Cycle Timing Parameters ID SD21 DQS–DQ Skew (defines the Data valid window in ...
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Signal Descriptions Table 43. SDHC Electrical DC Characteristics ID Parameter SD13 Supply Voltage (low voltage) SD14 Supply Voltage (high voltage) SD15 Power Up Time SD16 Supply Current Bus Signal Line Load SD17 Pull-up Resistance SD18 Open Drain Resistance Open Drain ...
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LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 43. SLCDC Timing Diagram—Serial Transfers to LCD Device Freescale Semiconductor tcss tcyc tds MSB trss ...
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Signal Descriptions Table 44. SLCDC Serial Interface Timing Parameters Symbol Parameter t Chip select setup time css t Chip select hold time csh t Serial clock cycle time cyc t Serial clock low pulse cl t Serial clock high pulse ...
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Table 45. SLCDC Parallel Interface Timing Parameters (continued) Symbol Parameter t Register select setup time rss t Register select hold time rsh 3.6.11 Synchronous Serial Interface (SSI) This section describes the electrical information of SSI. 3.6.11.1 SSI Transmitter Timing with ...
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Signal Descriptions SS2 DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 46. SSI Transmitter with Internal Clock Timing Diagram Table 46. SSI Transmitter with Internal Clock Timing ...
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Table 46. SSI Transmitter with Internal Clock Timing Parameters (continued) ID Synchronous Internal Clock Operation SS42 SRXD setup before (Tx) CK falling SS43 SRXD hold after (Tx) CK falling SS52 Loading • All the timings for the SSI are given ...
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Signal Descriptions SS2 DAM1_T_CLK (Output) DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_RXD (Input) SS48 DAM1_R_CLK (Output) Figure 48. SSI Receiver with Internal Clock Timing Diagram Table 47. SSI Receiver with Internal Clock Timing Parameters ID SS1 (Tx/Rx) CK clock period ...
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Table 47. SSI Receiver with Internal Clock Timing Parameters (continued) ID SS49 Oversampling clock rise time SS50 Oversampling clock low period SS51 Oversampling clock fall time All the timings for the SSI are given for a non-inverted serial clock polarity ...
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Signal Descriptions SS23 DAM1_T_CLK (Input) SS27 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 50. SSI Transmitter with External Clock Timing Diagram Table 48. SSI Transmitter with External Clock Timing ...
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All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the ...
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Signal Descriptions SS23 DAM1_T_CLK (Input) SS28 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_RXD (Input) Figure 52. SSI Receiver with External Clock Timing Diagram Table 49. SSI Receiver with External Clock Timing Parameters ID SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) ...
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All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the ...
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Signal Descriptions BCLK (for rising edge timing) BCLK (for falling edge timing) Address CS[ EB[x] LBA Output Data BCLK (for rising edge timing) Input Data DTACK ID WE1 Clock fall to address valid WE2 Clock rise/fall to address ...
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Table 50. WEIM Bus Timing Parameters (continued) ID WE5 Clock rise/fall to RW Valid WE6 Clock rise/fall to RW Invalid WE7 Clock rise/fall to OE Valid WE8 Clock rise/fall to OE Invalid WE9 Clock rise/fall to EB[x] Valid WE10 Clock ...
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Signal Descriptions Figure 54, Figure 55, Figure 34, accesses to external memory devices with the timing parameters mentioned in parameter settings. BCLK Last Valid Address ADDR CS[x] RW LBA OE EB[y] DATA Figure 54. Asynchronous Memory Timing Diagram for BCLK ...
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BCLK WE1 Last Valid Addr ADDR WE3 CS[x] RW WE11 LBA WE7 OE WE9 EB[y] ECB DATA Figure 56. Synchronous Memory Timing Diagram for Two Non-Sequential BCLK WE1 ADDR Last Valid Addr WE3 CS[x] WE5 RW WE11 LBA OE WE9 ...
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Signal Descriptions BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 CS[x] WE5 RW WE11 LBA OE WE9 EB[y] Figure 58. Muxed A/D Mode Timing Diagram for Asynchronous Write Access—WSC=7, LBA=1, LBN=1, LAH=1 BCLK WE1 ADDR/ Last Valid Addr M_DATA WE3 ...
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VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode 3.6.14.1 DAT_SE0 Bidirectional Mode Table 51. Signal Definitions—DAT_SE0 Bidirectional Mode Name USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 60. USB Transmit Waveform in DAT_SE0 Bidirectional Mode Figure 61. USB Receive Waveform in DAT_SE0 ...
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Signal Descriptions Table 52. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode Parameter Signal Name TX Rise/Fall Time USB_DAT_VP TX Rise/Fall Time USB_SE0_VM TX Rise/Fall Time USB_TXOE_B TX Duty Cycle USB_DAT_VP USB_DAT_VP Enable Delay USB_SE0_VM USB_DAT_VP Disable Delay USB_SE0_VM RX ...
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Figure 63. USB Receive Waveform in DAT_SE0 Unidirectional Mode Table 54. OTG Port Timing Specification in DAT_SE0 Unidirectional Mode Parameter Signal Name TX Rise/Fall Time USB_DAT_VP TX Rise/Fall Time USB_SE0_VM TX Rise/Fall Time USB_TXOE_B TX Duty Cycle USB_DAT_VP USB_DAT_VP Enable ...
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Signal Descriptions Figure 64. USB Transmit Waveform in VP_VM Bidirectional Mode Figure 65. USB Receive Waveform in VP_VM Bidirectional Mode 100 USB_SE0_VM i.MX27 and i.MX27L Data Sheet, Rev. 1.2 Preliminary—Subject to Change Without Notice USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM ...
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Table 56. OTG Port Timing Specification in VP_VM Bidirectional Mode Parameter Signal Name TX Rise/Fall Time USB_DAT_VP TX Rise/Fall Time USB_SE0_VM TX Rise/Fall Time USB_TXOE_B TX Duty Cycle USB_DAT_VP TX High Overlap USB_SE0_VM TX Low Overlap USB_SE0_VM USB_DAT_VP Enable Delay ...
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Signal Descriptions Figure 66. USB Transmit Waveform in VP_VM Unidirectional Mode Figure 67. USB Receive Waveform in VP_VM Unidirectional Mode 102 USB_SE0_VM i.MX27 and i.MX27L Data Sheet, Rev. 1.2 Preliminary—Subject to Change Without Notice USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_VP1 USB_VM1 ...
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Table 58. USB Timing Specification in VP_VM Unidirectional Mode Parameter Signal TX Rise/Fall Time USB_DAT_VP TX Rise/Fall Time USB_SE0_VM TX Rise/Fall Time USB_TXOE_B TX Duty Cycle USB_DAT_VP TX High Overlap USB_SE0_VM TX Low Overlap USB_SE0_VM USB_DAT_VP Enable Delay USB_SE0_VM USB_DAT_VP ...
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Package Information and Pinout 4 Package Information and Pinout The i.MX27/MX27L processor is available in a 17mm × 17mm, 0.65mm pitch, 404-pin MAPBGA package and a 19mm × 19mm, 0.8mm pitch, 473-pin MAPBGA package. 4.1 Full Package Outline Drawing (17mm ...
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Pin Assignments (17mm x 17mm) Table 59 identifies the pin assignments for the ball grid array (BGA) for full package. The connections of these pins depend solely upon the user application, however there are a few factory test signals ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) ATA_DATA10_ETMTRACEPKT9_PD12 ATA_DATA11_ETMTRACEPKT8_PD13 ATA_DATA12_ETMTRACEPKT7_PD14 ATA_DATA13_ETMTRACEPKT6_PD15 ATA_DATA14_ETMTRACEPKT5_PD16 ATA_DATA15_ETMTRACEPKT4_PF23 ATA_DATA4_ETMTRACEPKT14_PD6 ATA_DATA5_ETMTRACEPKT13_PD7 ATA_DATA7_ETMTRACEPKT12_PD9 ATA_DATA8_ETMTRACEPKT11_PD10 ATA_DATA9_ETMTRACEPKT10_PD11 106 Pin Name ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) CSPI2_MISO_USBH2_DATA2_PD23 CSPI2_MOSI_USBH2_DATA1_PD24 CSPI2_SCLK_USBH2_DATA0_PD22 Freescale Semiconductor Pin Name CLKMODE1 CLKO_PF15 CLS_PA25 CONTRAST_PA30 CS0 CS1 CS2 CS3 CS4_ETMTRACESYNC_PF21 CS5_ETMTRACECLK_PF22 CSI_D0_UART6_TXD_PB10 CSI_D1_UART6_RXD_PB11 CSI_D2_UART6_CTS_PB12 CSI_D3_UART6_RTS_PB13 CSI_D4_PB14 ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 108 Pin Name CSPI2_SS0_USBH2_DATA6_PD21 CSPI2_SS1_USBH2_DATA3_PD20 CSPI2_SS2_USBH2_DATA4_PD19 D0 D1 D10 D11 D12 D13 D14 D15 ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Pin Name FUSE VDD FUSEVSS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 110 Pin Name KP_ROW0 KP_ROW1 KP_ROW2 KP_ROW3 KP_ROW4 KP_ROW5 LBA LD0_PA6 LD1_PA7 LD10_PA16 LD11_PA17 LD12_PA18 LD13_PA19 LD14_PA20 LD15_PA21 ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Pin Name NFCLE_ETMTRACEPKT0_PF1 FRB_ETMTRACEPKT3_PF0 NFRE_ETMPIPESTAT1_PF5 NFWE_ETMPIPESTAT2_PF6 NFWP_ETMTRACEPKT1_PF2 N 1 VDD N 1 VDD N 10 VDD N 11 VDD N ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 112 Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Pin Name PC_POE_ATA_BUFFER_EN_PF7 PC_PWRON_ATA_DA2_PF16 PC_READY_ATA_CS0_PF17 PC_RST_ATA_RESET_PF10 PC_RW_ATA_IORDY_PF8 PC_VS1_ATA_DA1_PF14 PC_VS2_ATA_DA0_PF13 PC_WAIT_ATA_CS1_PF18 POR POWER_CUT POWER_ON_RESET PS_PA26 PWMO_PE5 Q VDD Q VDD Q ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 114 Pin Name RTCK_OWIRE_PE16 RTC VDD RTCVSS RW SD0 SD1 SD1_CLK_CSPI3_SCLK_PE23 SD1_CMD_CSPI3_MOSI_PE22 SD1_D0_CSPI3_MISO_PE18 SD1_D1_PE19 SD1_D2_PE20 SD1_D3_CSPI3_SS_PE21 SD10 SD11 ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Pin Name SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD3 SD3_CLK_ETMTRACEPKT15_PD1 SD3_CMD_PD0_ SD30 SD31 SD4 SD5 SD6 SD7 SD8 SD9 ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 116 Pin Name SSI1_RXDAT_PC21 SSI1_TXDAT_PC22 SSI2_CLK_GPT4_TIN_PC27 SSI2_FS_GPT5_TOUT_PC24 SSI2_RXDAT_GPT5_TIN_PC25 SSI2_TXDAT_GPT4_TOUT_PC26 SSI3_CLK_SLCDC2_CLK_PC31 SSI3_FS_SLCDC2_D0_PC28 SSI3_RXDAT_SLCDC2_RS_PC29 SSI3_TXDAT_SLCDC2_CS_PC30 SSI4_CLK_PC19 SSI4_FS_PC16 SSI4_RXDAT_PC17 SSI4_TXDAT_PC18 TCK ...
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Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) USBH1_RXDP_UART4_RXD_PB31 Freescale Semiconductor Pin Name UART3_TXD_PE8 UPLL VDD UPLLVSS USB_OC_PB24 USB_PWR_PB23 USBH1_FS_UART4_RTS_PB26 USBH1_OE_PB27 USBH1_RCV_PB25 USBH1_RXDM_PB30 USBH1_SUSP_PB22 USBH1_TXDM_UART4_TXD_PB28 USBH1_TXDP_UART4_CTS_PB29 USBH2_CLK_PA0 USBH2_DATA7_PA2_SUSPEND USBH2_DIR_PA1 USBH2_NXT_PA3 ...
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Package Information and Pinout Table 59. i.MX27 BGA (17 x 17) - Signal ID by Ball Grid Location (continued) 1. GND and QVSS contacts are tied together inside the BGA package 2. Freescale recommends tying GND and ...
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Pin Assignments (19mm x 19mm) Table 60 identifies the pin assignments for the ball grid array (BGA) for full package. The connections of these pins depend solely upon the user application, however there are a few factory test signals ...
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Package Information and Pinout Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) 120 Location Contact Name AA11 SD0 AA12 DQM0 AA13 SDCLK AA14 RW_B AA15 CS1_B AA16 EB0_B AA17 EXT_60M ...
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Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Location Contact Name AB3 SDQS2 AB4 SD21 AB5 SD19 AB6 SDQS1 AB7 SD14 AB8 SD10 AB9 SD5 AC10 A14 AC11 ...
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Package Information and Pinout Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) 122 Location Contact Name B17 UART1_CTS_PE14 B18 SD1_D0_CSPI3_MISO_PE18 B19 SD1_D2_PE20 B20 CSPI1_RDY_PD25 B21 CSPI1_SS0_PD28 B3 SD2_D1_MSHC_DATA1_PB5 B4 SD2_CMD_MSHC_BS_PB8 ...
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Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Location Contact Name C8 TIN_PC15 C9 SSI1_FS_PC20 D1 HSYNC_PA28 D10 SSI2_CLK_GPT4_TIN_PC27 D11 KP_ROW1 D12 KP_ROW5 D13 KP_COL0 D14 UART2_TXD_KP_COL6_PE6 D15 ...
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Package Information and Pinout Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) 124 Location Contact Name F1 LD13_PA19 F10 SSI2_TXDAT_GPT4_TOUT_PC26 F11 KP_ROW0 F12 I2C_DATA_PD17 F13 KP_COL1 F14 UART3_RXD_PE9 F15 TCK ...
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Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Location Contact Name H4 LD9_PA15 J1 LD0_PA6 J2 LD1_PA7 J20 USBOTG_DATA1_PC11 J21 USBOTG_DATA4_PC12 J22 USBOTG_DATA3_PC13 J23 USBH2_CLK_PA0 J3 LD2_PA8 J4 ...
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Package Information and Pinout Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) 126 Location Contact Name M22 POWER_ON_RESET M23 POWER_CUT M3 D12 M4 D13 M6 D11 N1 D10 N17 FPMVSS ...
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Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) Freescale Semiconductor Location Contact Name R23 ATA_DATA2_SD3_D2_PD4 R3 A13 R4 A12 T1 A11 T17 MPLLVSS T18 BOOT2 T2 A9 T20 ATA_DATA8_ETMTRACEPKT11_PD10 T21 ...
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Package Information and Pinout Table 60. i.MX27 BGA (19 x 19) - Signal ID by Ball Grid Location (continued) 128 Location Contact Name V2 A0 V20 BOOT1 V21 BOOT0 V22 ATA_DATA15_ETMTRACEPKT4_PF23 V23 ATA_DATA14_ETMTRACEPKT5_PD16 V3 SDBA0 V4 SD31 ...
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... Revision History Table 61 summarizes revisions to this document since the previous release. Rev. No. Date 1.2 7/2008 Corrected part number in section 1.3, “Ordering Information,” Part number previously listed as MCIMX27FVOP4A has been corrected to read MCIMX27VOP4A. 1.1 7/2008 Formatting and template work. Freescale Semiconductor Location Contact Name Y3 ...
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Revision History THIS PAGE INTENTIONALLY LEFT BLANK 130 i.MX27 and i.MX27L Data Sheet, Rev. 1.2 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
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Freescale Semiconductor i.MX27 and i.MX27L Data Sheet, Rev. 1.2 Preliminary—Subject to Change Without Notice Revision History 131 ...
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... Denver, Colorado 80217 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MCIMX27 Rev. 1.2 07/2008 Preliminary—Subject to Change Without Notice Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...