mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 50

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
3.5.5.1
VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on
VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC
is high.
parameters.
Figure 9
rising edge.
Figure 10
falling edge.
50
Figure 9
VSYNC
HSYNC
PIXCLK
DATA[7:0]
shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock
shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock
Gated Clock Mode Timing
Figure 9. CSI Timing Diagram, Gated, PIXCLK—Sensor Data at Falling Edge,
and
Figure 10
1
depict the gated clock mode timings of CSI, and
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
3
Latch Data at Rising Edge
Valid Data
2
4
Valid Data
5
7
6
Valid Data
Table 21
Freescale Semiconductor
lists the timing