AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 28

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

AD6624
Ch Address
A5
A6
A7
A8
A9
SCLK
SDFS
Figure 40. Serial Output Data Switching Characteristics
SDO
SCLK
Figure 42. Timing for Serial Output Port (SBM = 1)
Figure 39. Serial Input Data Timing Requirements
SDO
Figure 41. SDFS Timing Requirements (SBM = 0)
SCLK
SCLK
SDFS
SDI
RISING SCLK AFTER SDFS GOES HIGH
FIRST DATA IS AVAILABLE THE FIRST
Register
BIST Signature for I Path
BIST Signature for Q Path
# of BIST Outputs to Accumulate
RAM BIST Control Register
Serial Port Control Register
t
t
SSF
DSDO
t
SSI
DATA
I
15
t
DSO
t
HSI
t
HSF
Table VIII. Channel Address Memory Map (continued)
I
14
I
MSB
SDFS MINIMUM
WIDTH IS ONE SCLK
I
13
I
MSB1
–28–
Bit Width
16
16
20
3
10
SBM0
SBM0 is the Serial Bus Master pin for the Channel 0 Serial Port
only. Serial Ports 1, 2, and 3 will always default to Serial Slave
mode but can be programmed as masters in the internal register
space. The SBM0 pin gives the user the option to boot the
AD6624 through Serial Port 0 as a master. When SBM0 is high
(master mode), the AD6624 generates SCLK0 and SDFS0.
When SBM0 is low (slave mode), the AD6624 accepts external
SCLK0 and SDFS0 signals. When configured as a bus master,
the SCLK0 signal can be used to strobe data into the DSP inter-
face. When used with another AD6624 in Serial Cascade mode,
SCLK0 can be taken from the master AD6624 and used to shift
data out from the cascaded device. In this situation, SDFS of
the slave AD6624 channel is connected to the SDFE pin of the
master AD6624 channel (or the preceding chip in the chain).
When an AD6624 is in Serial Slave mode, all of the serial port
activities are controlled by the external signals SCLK and SDFS.
Figure 43. Serial Frame Switching Characteristics (SBM = 1)
SCLK
SCLK
SDFE
SDFS
SDFE
SDO
Figure 44. SDO, SDFE Switching Characteristics
Comments
BIST-I
BIST-Q
19–0: # of Outputs (Counter Value Read)
2:
1:
0:
9:
8–7:
6–5:
4:
3–0:
t
DSDFS
I
t
15
DSDO
D-RAM Fail/Pass
C-RAM Fail/Pass
RAM BIST Enable
Map RCF Data to BIST Registers
I_SDFS Control
1x:
01:
00:
SOWL
1x:
01:
00:
SBMx
SDIVx[3:0]
Separate I and Q SDFS Pulses
SDFS High for Entire Frame
Single SDFS Pulse
24-Bit Words
16-Bit Words
12-Bit Words
I
14
Q
1
t
t
DSDFE
DSDFE
Q
0
REV. B