AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 32

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

AD6624
Bit 8 is used as an extra address to allow a second block of 128
words of CMEM to be addressed by the channel addresses at
0x00–0x7F. If this bit is 0, the first 128 words are written and if
this bit is 1, a second 128 words is written. This bit is only used
to program the Coefficient Memory. It is not used in any way by
the processing and filters longer than 128 taps can be performed.
Bit 7 is used to help control the output formatting of the AD6624’s
RCF data. This bit is only used when the 8 + 4 or 12 + 4 floating-
point modes are chosen. These modes are enabled by Bits 5 and
4 of this register below. When this bit is 0, the I and Q output
exponents are determined separately based on their individual
magnitudes. When this bit is 1, the I and Q data is a complex
floating-point number where I and Q use a single exponent that
is determined based on the maximum magnitude of I or Q.
Bit 6 is used to force the Output Scale Factor in Bits 3–0 of this
register to be used to scale the data even when one of the Float-
ing Point Output modes is used. If the number is too large to
represent with the Output Scale chosen, the mantissas of the I
and Q data clip and do not overflow.
Bits 5 and 4 choose the output formatting option used by the
RCF data. The options are defined in Table X and are dis-
cussed further in the Output Format section of the data sheet.
Bit Values
1x
01
00
Bits 3–0 of this register represent the Output Scale Factor of the
RCF. They are used to scale the data when the output format is
in fixed-point mode or when the Force Exponent bit is high.
0xA5: BIST Register for I
This register serves two purposes. The first is to allow the com-
plete functionality of the I data path in the channel to be tested
in the system. The BIST section of the data sheet should be
consulted for further details. The second function is to provide
access to the I output data through the microport. To accom-
plish this, the Map RCF data to BIST bit in the Serial Port
Control register, 0xA9, should be set high. Sixteen-bits of I data
can then be read through the microport in either the 8 + 4, 12 + 4,
12-bit linear or 16-bit linear output modes. This data may come
from either the formatted RCF output or the CIC5 output.
0xA6: BIST Register for Q
This register serves two purposes. The first is to allow the com-
plete functionality of Q data path in the channel to be tested in
the system. The BIST section of the data sheet should be con-
sulted for further details. The second function is to provide access
to the Q output data through the microport. To accomplish this,
the Map RCF data to BIST bit in the Serial Port Control regis-
ter, 0xA9, should be set high. Sixteen bits of Q data can then be
Channel
0
1
2
3
Table IX. RCF Input Configurations
12-Bit Mantissa and 4-Bit Exponent (12 + 4)
8-Bit Mantissa and 4-Bit Exponent (8 + 4)
Fixed-Point Mode
Output Option
Table X. Output Formats
RCF Input Source when Bit 9 is 1
1
0
1
1
–32–
read through the microport in either the 8 + 4, 12 + 4, 12-bit
linear, or 16-bit linear output modes. This data may come from
either the formatted RCF output or the CIC5 output.
0xA7: BIST Control Register
This register controls the number of outputs of the RCF or CIC
filter that are observed when a BIST test is performed. The BIST
signature registers at addresses 0xA5 and 0xA6 will observe this
number of outputs and then terminate. The loading of these
registers also starts the BIST engine running. Details of how to
utilize the BIST circuitry are defined in the BIST section of the
data sheet.
0xA8: RAM BIST Control Register
This register is used to test the memories of the AD6624 should
they ever be suspected of a failure. Bit 0 of this register is written
with a one when the channel is in SLEEP and the user waits for
1600 CLKs and then polls the bits. If Bit 1 is high, the CMEM
failed the test; if Bit 2 is high, the data memory used by the
RCF failed the test.
0xA9: Serial Port Control Register
This register controls the serial port of the AD6624 and, along
with the RCF control register, it helps to determine the out-
put format.
Bit 9 of this register allows the RCF or CIC5 data to be mapped
to the BIST registers at addresses 0xA5 and 0xA6. When this
bit is 0, the BIST register is in signature mode and ready for a
self-test to be run. When this bit is 1, the output data from
the RCF after formatting or the CIC5 data is mapped to these
registers and can be read through the microport. In addition,
when this bit is high, the DR pin for the channel delivers a
1 CLK cycle wide pulse that can be used to synchronize the
host processor with the AD6624. This signal is a 1 SCLK cycle
wide pulse when this bit is 0.
Bits 8 and 7 control the output format of the SDFS pulse.
When these bits are 00, there is a single SCLK cycle wide pulse
for the I and Q data. When these bits are 01, the SDFS signal is
high for all of the bits shifted during the serial frame. When
these bits are 10 or 11, there are two SDFS pulses that are each
1 SCLK cycle wide. One pulse precedes the I word of data and
the second precedes the Q word of data. When a serial port is
configured as a serial slave, it should be in the first mode with
these bits set to 00.
Bits 6 and 5 determine the serial word length used by the serial
port. If these bits are 00, the serial ports use 12-bit words and
shift 12 bits of I followed by 12 bits of Q with each shifted MSB
first. If these bits are 01, the serial ports use 16-bit words and
shift 16 bits of I followed by 16 bits of Q with each shifted MSB
first. If these bits are 1x, the serial ports use 24-bit words and
shift 24 bits of I followed by 24 bits of Q with each shifted MSB
first. When the fixed point output option is chosen from the
RCF control register, these bits also set the rounding correctly
in the output formatter of the RCF.
Bit 4 of this register controls whether the Serial Port is a master
or slave. This register powers up low so that the serial port is a
slave in order to avoid contention problems on the output driv-
ers. The serial port for channel 0 does not use this bit. The
master/slave status of Serial Port 0 is set by the SBM0 pin.
Bits 3–0 control the rate of the SCLK signal when the channel is
master. This four-bit bus can set the SCLK as a division of the
master CLK from 1 to 16 with approximately a 50% duty cycle.
REV. B