W83627THF Nuvoton Technology Corporation of America, W83627THF Datasheet - Page 108

• Manufacturer Part Number: W83627THF
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627THF

• Pin Count: 128
• Lead Free Status / RoHS Status: Not Compliant

CRF9 (Default 0x00)
CRFE, FF (Default 0x00)
Reserved for Winbond test.
7.3
CR30 (Default 0x00)
CR60, CR 61 (Default 0x00, 0x00)
These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00)
Bit 0
Bit 7 - 3 : Reserved. Return zero when read.
Bit 2
Bit 1
Bit 0
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit 3 - 0 : These bits select IRQ channel for Hardware Monitor.
Logical Device B (Hardware Monitor)
: IRQIN0EN.
= 0 disable the generation of an SMI / PME interrupt due to IRQIN0's IRQ.
= 1 enable the generation of an SMI / PME interrupt due to IRQIN0's IRQ.
: PME_EN: Select the power management events to be either an PME or SMI
interrupt for
the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1.
= 0 the power management events will generate an SMI event
= 1 the power management events will generate an PME event.
: FSLEEP: This bit selects the fast expiry time of individual devices.
= 0 1 second.
= 1 8 mS
: SMIPME_OE: This is the SMI and PME output enable bit.
= 0 neither SMI nor PME will be generated. Only the IRQ status bit is set.
= 1 an SMI or PME event will be generated.
= 1 Activates the logical device.
= 0 Logical device is inactive.
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W83627THF/W83627THG
Publication Release Date: September 26, 2006
Revision 1.2