W83627THF Nuvoton Technology Corporation of America, W83627THF Datasheet - Page 65

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W83627THF

Manufacturer Part Number
W83627THF
Description
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627THF

Pin Count
128
Lead Free Status / RoHS Status
Not Compliant

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Bit 2: VIN1 Voltage Status. Set 1, the voltage of VIN1 is over the limit value. Set 0, the voltage of
Bit 1: VIN0 Voltage Status. Set 1, the voltage of VIN0 is over the limit value. Set 0, the voltage of
Bit 0: VCORE Voltage Status. Set 1, the voltage of VCORE is over the limit value. Set 0, the
5.8.52 Real Time Hardware Status Register II -- Index 5Ah (Bank 4)
Register Location:
Power on Default Value
Attribute:
Size:
Bit 7: Smart CPUFANIN warning status. Set 1, the CPUTIN temperature has been over the target
Bit 6: Smart SYSFANIN warning status. Set 1, the SYSTIN temperature has been over the target
Bit 5: AUXTIN temperature sensor status. Set 1, the temperature exceeds the over-temperature limit
Bit 4: Case Open Status. Set 1, the case open is detected and latched. Set 0, the case is not latched
Bit 3: CPUFANIN Status. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed
Bit 2-1: Reserved.
Bit 0: VIN2 Voltage Status. Set 1, the voltage of VIN2 is over the limit value. Set 0, the voltage of
5.8.53 Real Time Hardware Status Register III -- Index 5Bh (Bank 4)
Register Location:
Power on Default Value
Attribute:
Size:
temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan
temperature does not reach the warning range yet.
temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan
temperature does not reach the warning range yet.
value. Set 0, the temperature is in under the hysteresis value.
open.
counter is in the limit range.
VIN1 is in the limit range.
VIN0 is in the limit range.
voltage of VCORE is in the limit range.
VIN2 is in the limit range.
7
5Ah
00h
Read Only
8 bits
5Bh
00h
Read Only
8 bits
6
5
4
3
- 58 -
2
1
W83627THF/W83627THG
0
VIN2_STS
Reserved
Reserved
AUXFANIN_STS
CASE_STS
AUXTIN_STS
TAR1_STS
TAR2_STS
TM
TM
. Set 0, the
. Set 0, the

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