NH82801HBM S LA5Q Intel, NH82801HBM S LA5Q Datasheet - Page 30

• Manufacturer Part Number: NH82801HBM S LA5Q
• Manufacturer: Intel

Specifications of NH82801HBM S LA5Q

• Lead Free Status / RoHS Status: Compliant

13.
14.
Intel
®
ICH8 Family Specification Update
Datasheet with the Ball Names listed below for the following Ball Numbers.
Correct section 11.1.43 CIR5 - Chipset Initialization Register 5 in the EDS and
Datasheet
11.1.43 CIR5—Chipset Initialization Register 5
Default Value:
9.1.21 GEN1_DEC-LPC I/F Generic Decode Range 1 Register
(LPC I/F-D31:F0)
Offset Address:84h–87h
Default Value:00000000h
Correct the Ball Names in Figure 20 and Figure 21 Ballout (Mobile Only) in the
Offset Address:
Correct Figure 20 and Figure 21 Ballout information
Correct section 11.1.43 bit 0 definition
AG29
C22
C23
AJ6
AJ26
D5
W23
AJ10
AH10
31:24
23:18
17:16
15:2
Bit
1
0
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for
decoding blocks up to 256 bytes in size.
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W.
is aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The ICH Does not provide decode down to the word or byte level.
Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F.
Ball#
1D40h–1D47h
0000000000000000h
CPUPWRGD/GPIO49
LAN_RXD2
SPI_CLK
VccSATAPLL
SMBCLK
VCC3_3
VCC1_5_A
SATA1GP/GPIO19
VSS
Attribute:
Size:
Power Well:
Change Ball Name to:
Description
Reserved
32 bit
R/W
Core
Attribute:
Size:
R/W, R/WL
64-bit
This address
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