NH82801BA S L7UU Intel, NH82801BA S L7UU Datasheet - Page 632
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NH82801BA S L7UU
Manufacturer Part Number
NH82801BA S L7UU
Description
Manufacturer
Intel
Datasheet
1.NH82801BA_S_L7UU.pdf
(671 pages)
Specifications of NH82801BA S L7UU
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Compliant
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Testability
21.2
21.3
21.3.1
632
Figure 28. Example XOR Chain Circuitry
Table 197. XOR Test Pattern Example
Tri-State Mode
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including the XOR
Chain outputs.
XOR Chain Mode
In the ICH5, provisions for Automated Test Equipment (ATE) board level testing are implemented
with XOR Chains. The ICH5 signals are grouped into four independent XOR chains which are
enabled individually. When an XOR chain is enabled, all output and bi-directional buffers within
that chain are tri-stated, except for the XOR chain output. Every signal in the enabled XOR chain
(except for the XOR chain’s output) functions as an input. All output and bi-directional buffers for
pins not in the selected XOR chain are tri-stated.
circuitry.
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity
(e.g., opens and shorts to VCC or GND). An example algorithm to do this is shown in
In this example, Vector 1 applies all 0s to the chain inputs. The outputs being non-inverting will
consistently produce a 1 at the XOR output on a good board. One short to VCC (or open floating to
VCC) will result in a 0 at the chain output, signaling a defect.
Likewise, applying Vector 7 (all 1s) to the chain inputs (given that there are an even number of
input signals in the chain), will consistently produce a 1 at the XOR chain output on a good board.
One short to VSS (or open floating to VSS) will result in a 0 at the chain output, signaling a defect.
Vector
1
2
3
4
5
6
7
Vcc
Input
Pin 1
Input
Pin 1
0
1
1
1
1
1
1
Input
Pin 2
Input
Pin 2
0
0
1
1
1
1
1
Input
Pin 3
Input
Pin 3
0
0
0
1
1
1
1
Input
Pin 4
Intel
Figure 28
Input
Pin 4
®
0
0
0
0
1
1
1
82801EB ICH5 / 82801ER ICH5R Datasheet
Input
Pin 5
is a schematic example of XOR chain
Input
Pin 5
0
0
0
0
0
1
1
Input
Pin 6
Input
Pin 6
0
0
0
0
0
0
1
Output
Chain
XOR
Table
Output
XOR
1
0
1
0
1
0
1
197.
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