RG82845 S L5V7 Intel, RG82845 S L5V7 Datasheet - Page 53
RG82845 S L5V7
Manufacturer Part Number
RG82845 S L5V7
Description
Manufacturer
Intel
Datasheet
1.RG82845_S_L5V7.pdf
(148 pages)
Specifications of RG82845 S L5V7
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3.5.16
Intel
®
82845 MCH for SDR Datasheet
R
DRA—DRAM Row Attribute Registers (Device 0)
Offset:
Default:
Access:
Size:
The DRAM Row Attribute Register defines the page sizes to be used when accessing different
pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of
rows:
Row 0, 1 = 70h
Row 2, 3 = 71h
Row 4, 5 = 72h (Used for SDRAM configuration only)
Row 6, 7 = 73h (RAODD and RAEVEN fields must contain default value of 00h)
Rsvd
Rsvd
Rsvd
Rsvd
7
7
7
7
6
6
6
6
Row attribute for Row 1
Row attribute for Row 3
Row attribute for Row 5
Row attribute for Row 7
70–73h (DRA0–DRA3)
00h
R/W
8 bits
4
4
4
4
Rsvd
Rsvd
Rsvd
Rsvd
3
3
3
3
2
2
2
2
Row Attribute for Row 0
Row Attribute for Row 2
Row Attribute for Row 4
Row Attribute for Row 6
Register Description
0
0
0
0
53
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