RG82845 S L5V7 Intel, RG82845 S L5V7 Datasheet - Page 86
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RG82845 S L5V7
Manufacturer Part Number
RG82845 S L5V7
Description
Manufacturer
Intel
Datasheet
1.RG82845_S_L5V7.pdf
(148 pages)
Specifications of RG82845 S L5V7
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Register Description
3.6.11
3.6.12
86
SBUSN1—Secondary Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
This register identifies the bus number assigned to the second bus side of the “virtual” PCI-PCI
bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to AGP.
SUBUSN1—Subordinate Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
This register identifies the subordinate bus (if any) that resides at the level below AGP. This
number is programmed by the PCI configuration software to allow mapping of configuration
cycles to AGP.
Bit
7:0
Bit
7:0
Bus Number. Programmable. Default = 00h.
Bus Number. Programmable. Default = 0.
19h
00h
R/W
8 bits
1Ah
00h
R/W
8 bits
Descriptions
Descriptions
Intel
®
82845 MCH for SDR Datasheet
R
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