FDC37M707-MS Standard Microsystems (SMSC), FDC37M707-MS Datasheet
FDC37M707-MS
Specifications of FDC37M707-MS
Related parts for FDC37M707-MS
FDC37M707-MS Summary of contents
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... Super I/O Controller with Wake-Up Features 5 Volt Operation PC98/99 and ACPI 1.0 Compliant ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management - Shadowed Write-Only Registers - Programmable Wake-up Event Interface System Management Interrupt, Watchdog Timer 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk ...
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ISA Host Interface - 16 Bit Address Qualification - 8 Bit Data Bus - IOCHRDY for ECP and IrCC - Three 8 Bit DMA Channels - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - PCI PME ...
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FEATURES ....................................................................................................................................... 1 GENERAL DESCRIPTION................................................................................................................. 4 DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 6 DESCRIPTION OF MULTIFUNCTION PINS .................................................................................... 10 REFERENCE DOCUMENTS ........................................................................................................... 10 FUNCTIONAL DESCRIPTION ......................................................................................................... 12 SUPER I/O REGISTERS ................................................................................................................. 12 HOST PROCESSOR INTERFACE................................................................................................... 12 FLOPPY DISK CONTROLLER ........................................................................................................ 13 ...
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The FDC37M70x with IrDA incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550A compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip bus ...
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DRVDEN0 1 DRVDEN1 2 3 nMTR0 nPME 4 nDS0 5 6 P17 VSS 7 8 nDIR nSTEP 9 10 nWDATA 11 nWGATE nHDSEL 12 FDC37M70x 13 nINDEX 14 nTRK0 15 nWPRT 16 100 PIN QFP nRDATA 17 nDSKCHG 18 VTR ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME PROCESSOR/HOST INTERFACE (36) 45:42, System Data Bus 40:37 31:21 11-bit System Address Bus 20 Chip Select/SA11 (Note 1) 34 Address Enable 55 I/O Channel Ready 46 ISA Reset Drive 33 Serial IRQ 32 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME 18 Trickle Voltage 16 Read Disk Data 11 Write Gate 10 Write Disk Data 12 Head Select 8 Step Direction 9 Step Pulse 17 Disk Change 5 Drive Select 0 3 Motor On ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./QFP NAME 92 Ring Indicator 2/8042 P16 PARALLEL PORT INTERFACE (17) 75:68 Parallel Port Data Bus 66 Printer Select 67 Initiate Output 83 Auto Line Feed 82 Strobe Signal 81 Busy Signal 77 Acknowledge Handshake ...
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I Input, TTL compatible IS Input with Schmitt trigger IOD16 Input/Output, 16mA sink IO24 Input/Output, 24mA sink, 12mA source IO4 Input/Output, 4mA sink, 2mA source O4 Output, 4mA sink, 2mA source O24 Output, 24mA sink, 12mA source OD24 Output, Open ...
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PIN ORIGINAL NO./QFP FUNCTION nDACK3 51 52 DRQ3 nRI2 92 nDCD2 94 RXD2 95 96 TXD2 nDSR2 97 nRTS2 98 nCTS2 99 100 nDTR2 Note 1: Controlled by DMA3SEL(LD8:CRC0.1) Note 2: Controlled by 8042COMSEL(LD8:CRC0.3) Note 3: Controlled by IR Option ...
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PME SMI SER_IRQ SERIAL PCI_CLK IRQ nIOR nIOW AEN * SA[0:12] (nCS) * SA[13-15] HOST CPU SD[O:7] INTERFACE * DRQ[1:3] * nDACK[1:3] TC RESET_DRV IOCHRDY CLOCK GEN nINDEX V Vcc Vss nTRK0 TR nDSKCHG nWRPRT CLOCKI nWGATE 14MHz FIGURE ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via ...
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The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drive. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible ...
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Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In ...
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INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT ...
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Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 andModel 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data ...
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RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported in the FDC37M70x. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported in the FDC37M70x. BIT 2 ...
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Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of contains the enable for the DMA logic and a software reset bit. unaffected by a software reset. The DOR can be written to at any time. 7 ...
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Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to TAPE SEL1 (TDR. Table ...
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Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode ...
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Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) not the DSR, for PC/AT ...
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PRECOMP PRECOMPENSATION 432 DELAY (nsec) <2Mbps 111 0.00 001 41.67 010 83.34 011 125.00 100 166.67 101 208.33 110 250.00 000 Default Default: See Table 12 *2Mbps data rate is only available 2Mbps* 0 20.8 41.7 62.5 ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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DATA RATE *The 2Mbps data rate is only available if V MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be ...
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Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits in the Main ...
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Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in a high impedance state during ...
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DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data ...
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Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 for the appropriate values. ...
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During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check ...
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BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable WP pin became a "1" while the FDC is executing ...
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BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. This bit is always "0". Any ...
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BIT NO. SYMBOL Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a ...
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This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. Model 30 mode - (IDENT low, MFM ...
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FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 ...
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The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of-track functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If ...
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Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, ...
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Table 17 - Description of Command Symbols SYMBOL NAME H/HDS Head Address Selected head (disk side encoded in the sector ID field. HLT Head Load The time interval that FDC waits after loading ...
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Table 17 - Description of Command Symbols SYMBOL NAME OW Overwrite The bits D0-D3 of the Perpendicular Mode Command can only be modified set defined in the Lock command. PCN Present The current ...
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PHASE R Command W MT MFM Execution Result Table 18 - Instruction Set READ DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 -------- ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied seek will be ...
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FDC, the ID information in the result phase is dependent upon the state of the MT bit and EOT byte. Refer to Table 20. At the completion of the Read Data command, the head is not unloaded until ...
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DATA ADDRESS SK BIT MARK TYPE VALUE ENCOUNTERED SECTOR READ? 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data RESULTS CM BIT OF DESCRIPTION ST2 SET? OF RESULTS Yes No Normal termination. Yes Yes Address not incremented. ...
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This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 22 - Skip Bit vs. Read Deleted Data Command DATA ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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By setting the EC bit to "1", an implicit TC will be issued to the FDC. This implicit TC will occur when the SC value has decremented to 0 (an SC ...
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The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per the IBM System ...
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FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 5.25" 4096 ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512** 1024 GPL1 = suggested GPL values in Read and Write ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Seek command - Step to the proper track 2) Sense Interrupt Status Terminate the Seek command 3) Read ID - Verify head is on proper track 4) Issue Read/Write command. The Seek ...
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Sense Drive Status obtains information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values for each of ...
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The Configure command is issued to select the special features of the FDC. command need not be issued if the default values of the FDC meet requirements. Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL ...
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The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the FDC starts counting from 0 again as the ...
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync ...
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WGATE GAP LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO the LOCK Command has been added. This command should only be ...
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The FDC37M70x incorporates two full function UARTs. They are compatible NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to- parallel conversion on received characters and parallel-to-serial conversion characters. The data rates are independently programmable from 460.8K baud ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 2 Setting this bit to a logic ...
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Table 30 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT Highest Second Second ...
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Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each transmitted or received serial ...
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This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that described above for bit 0. Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not ...
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Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop bit following the last data bit or parity bit is detected as ...
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Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was read. Bit 2 Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed ...
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C. The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) interrupt. D. The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the ...
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With FCR bit 0 = "1" resetting IER bits all to zero puts the UART in the FIFO Polled Mode of operation. Since the RCVR and XMITTER are controlled separately, either one or both ...
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REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) RESET/Read LSR INTRPT (RCVR Data Ready) ...
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REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt Enable Register DLAB = 0 ADDR = 2 Interrupt Ident. ...
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BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) Interrupt ID Interrupt ID 0 Bit ...
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FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as soon as the CPU ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA 1.0, and Amplitude Shift Keyed IR. The IR transmission can ...
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The FDC37M70x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to ...
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AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data Register latches the contents ...
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This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means ...
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When the EPP mode is selected in the configuration register, the standard and bi- directional modes are also available EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional ...
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The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. IOCHRDY is driven active low at the start of each EPP read and is released when it has been determined that the read cycle ...
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The host sets PDIR bit in the control register to a logic "0". nWRITE. 2. The host selects an EPP register, places data on the SData bus and drives nIOW active. 3. The chip places address or data on ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional ...
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This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ...
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NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the ...
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The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition to Table 37 - ECP Register Definitions NAME ADDRESS ...
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ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data Register latches the ...
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Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. ...
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Refer to Table 39B. BITS [2:0] Parallel Port DMA (read-only) Refer to Table 39C. ecr (Extended Control Register) ADDRESS OFFSET = 402H Mode = all This register controls the extended ECP parallel port functions. BITS 7,6,5 These bits are Read/Write ...
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R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in ...
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Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP ...
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ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8 bit data or 8 bit commands. When in the forward direction, normal data is ...
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The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert. ...
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DMA transfers is with a TC.) DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the ...
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FIFO in a single burst. Programmed I/O - Transfers from the Host to the FIFO In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in ...
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The Floppy Disk Control signals are available optionally on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These modes can be selected in the ...
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CONNECTOR QFP PIN # CHIP PIN # SPP MODE ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management Direct power management ...
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An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as V and off. When the internal PWRGOOD signal is “1” (active > 3.7V, and the FDC37M70x cc host interface ...
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AVAILABLE REGISTERS BASE + ADDRESS PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR 07H CCR Access to these registers wakes up ...
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SYSTEM PINS STATE IN AUTO POWERDOWN INPUT PINS nIOR Unchanged nIOW Unchanged SA[0:9] Unchanged SD[0:7] Unchanged RESET_DRV Unchanged DACKx Unchanged TC Unchanged OUTPUT PINS IRQx Unchanged (low) SD[0:7] Unchanged DRQx Unchanged (low) 107 ...
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All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS nRDATA nWPROT nTR0 nINDEX ...
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Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter enters auto powerdown when ...
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SERIAL INTERRUPTS The FDC37M70x will support the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. A) Start Frame timing with source sampled a ...
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IRQ14 IRQ15 FRAME FRAME PCICLK IRQSER None IRQ15 Driver 1) Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode. 2) There may be none, one or more Idle states ...
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There are two modes of operation for the IRQSER Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the IRQSER is Idle. driving low for one clock ...
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IRQSER PERIOD The Serial IRQ data frame will now support IRQ2 from a logical device, previously IRQSER Period 3 was reserved for use by ...
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Once all IRQ/Data Frames have completed the Host Controller will terminate IRQSER activity by initiating a Stop Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the IRQSER is low for two or ...
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The Watchdog Timer Control, SMI Enable and SMI Status Registers can be accessed by the host when the chip is in the normal run mode if CR03 Bit[7]=1. The host uses GP Index and Data register to access these registers. ...
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INDEX 0x01 0x02 0x03 Access to Watchdog Timer Control (L8 - CRF4) 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Access to SMI Enable Register 1 (L8-CRB4) 0x0D Access to SMI Enable Register 2 (L8-CRB5) 0x0E Access to SMI ...
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The FDC37M70x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be mapped to an interrupt WDT_CFG Configuration Register. The FDC37M70x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, ...
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The FDC37M70x is a Super I/O and Universal Keyboard Controller that is intelligent keyboard management in desktop computer applications. The Super I/O supports a Floppy Disk Controller, two 16550 type serial ports one ECP/EPP Parallel Port. 8042A P27 P10 P26 ...
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The FDC37M70x ISA interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data bus; the nIOR, nIOW and the Status register, ISA ADDRESS nIOW 0x60 0 1 0x64 0 1 Note 1: These registers ...
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This bit write only register. written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. Keyboard Data Read This bit read only register. If enabled ...
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INTERFACE Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37M70x provides four signal pins that may be ...
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Status Register This register is cleared on a reset. This register is read-only for the Host and read/write by the FDC37M70x CPU. UD Writable by FDC37M70x CPU. These bits are user-definable. C/D (Command Data)-This ...
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The FDC37M70x provides two options for GateA20 and Keyboard Reset: 8042 Software Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET. Bit Function 7:6 Reserved. Returns 00 when read 5 Reserved. Returns a 1 when read 4 Reserved. ...
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CPU under program control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means of resetting the CPU. This provides a faster means of ...
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CPU low for support of real mode compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to control the nA20M input of the CPU. Writing ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 Gate A20 Turn-On Sequence Timing When writing to the command and data port with hardware speedup, the ...
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The FDC37M70x implements a group nSMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for transparent management. The nSMI group interrupt output consists of the enabled interrupts from each of the functional ...
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The Configuration of the FDC37M70x is very flexible and is based on the configuration architecture implemented in typical Plug-and- Play components. The FDC37M70x is designed for motherboard applications in which the resources required by their components are known. With its ...
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To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip into the Configuration State the Config Key is sent ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,3F0H MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, ; LOGICAL DEVICE 8 ;----------------------------' MOV DX,3F0H ...
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SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 52 – FDC37M70x Configuration Registers Summary HARD VCC INDEX TYPE RESET POR ...
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HARD VCC INDEX TYPE RESET POR 0xF0 R/W 0x0E 0x0E 0xF1 R/W 0x00 0x00 0xF2 R/W 0xFF 0xFF 0xF4 R/W 0x00 0x00 0xF5 R/W 0x00 0x00 LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE ...
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HARD INDEX TYPE RESET LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED) LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD) 0x30 R/W 0x00 0x70 R/W 0x00 0x72 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Aux I/O) 0x30 R/W 0x00 0xB4 R/W ...
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Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits REGISTER ADDRESS 0x00 - 0x01 Config Control 0x02 W Default ...
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REGISTER ADDRESS Card Level 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Reserved Device ID 0x20 R Hard wired = 0x42 Device Rev 0x21 R Hard wired = Current Revision PowerControl 0x22 R/W Default = 0x00. on ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04, on Vcc POR or Reset_Drv hardware signal. Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= Vcc POR or Reset_Drv Configuration ...
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REGISTER ADDRESS TEST 5 0x2C R/W Default = 0x00, on Vcc POR TEST 1 0x2D R/W Default = 0x00, on Vcc POR TEST 2 0x2E R/W Default = 0x00, on Vcc POR TEST 3 0x2F R/W Default = 0x00, on ...
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Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, Serial 2, Keyboard ...
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Table 55 - Logical Device Registers LOGICAL DEVICE REGISTER ADDRESS Interrupt Select (0x70,0x72) Defaults : 0x70 = 0x00, on Vcc POR or Reset_Drv 0x72 = 0x00, on Vcc POR or Reset_Drv (0x71,0x73) DMA Channel Select (0x74,0x75) Default = 0x04 on ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x00 FDC 0x60,0x61 (Note 4) 0x03 Parallel 0x60,0x61 Port 0x04 Serial Port 0x60,0x61 1 0x05 Serial Port 0x60,0x61 2 0x62,0x63 0x06 Reserved 0x07 KYBD ...
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Table 56 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX 0x09 Reserved Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical devices. Table 57 ...
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NAME REG INDEX DMA Channel 0x74 (R/W) Select Default = 0x04 on Vcc POR or Reset_Drv Note: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND : For the FDC logical device by setting ...
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IRQ and DMA Enable and Disable: Any time the IRQ or DACK for a logical block is disabled by a register bit in that logical block, the IRQ and/or DACK must be disabled. This is in addition to the ...
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The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the RESET_DRV signal. These registers are not affected by soft resets. Table 59 - Floppy ...
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Table 59 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD Type Register 0xF2 R/W Default = 0xFF on Vcc POR or Reset_Drv 0xF3 R FDD0 0xF4 R/W Default = 0x00 on Vcc ...
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Table 60 - Parallel Port, Logical Device 3 [Logical Device Number = 0x03] NAME REG INDEX PP Mode Register 0xF0 R/W Default = 0x3C on Vcc POR or Reset_Drv PP Mode Register 2 0xF1 R/W Default = 0x00 on Vcc ...
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Table 61 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on Vcc POR or Reset_Drv Note 1: To properly share and IRQ, 1. ...
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Table 62 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on Vcc POR or Reset_Drv IR Half Duplex 0xF2 Timeout Default = 0x03 on Vcc ...
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Table 63 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 R/W Default = 0x00 on Vcc POR or Reset_Drv 0xF1 - 0xFF Table 64 - Auxiliary I/O, Logical Device 8 [Logical Device Number ...
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NAME REG INDEX SMI Enable 0xB5 R/W Register 2 Default = 0x00 on Vcc POR SMI Status 0xB6 R/W Register 1 Default = 0x00 on Vcc POR SMI Status 0xB7 R/W Register 2 Default = 0x00 on Vcc POR Default ...
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NAME REG INDEX Pin Multiplex 0xC0 Controls Default = 0x02 on Vcc POR Force Disk Change 0xC1 Default = 0x03 on (R/W) Vcc POR Floppy Data Rate 0xC2 Select Shadow (R) UART1 FIFO 0xC3 Control Shadow UART2 FIFO 0xC4 Control ...
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NAME REG INDEX PME Status 0xC6 Default = 0x00 on (R/w Clear) POR V TR PME Wake Status 0xC7 Default = 0x00 on (R/w Clear) V POR TR DEFINITION Bit[0] PME_Status = 0 (default Set when FDC37M70x would ...
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NAME REG INDEX PME Wake Enable 0xC8 Default = 0x00 on (R/W) V POR TR DEFINITION This register is used to enable individual FDC37M70x PME wake sources onto the nPME wake bus. When the PME Wake Enable register bit for ...
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MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nRTS2 0 1 Table 66 - nCTS2 MUXING MUX CONTROL PIN 16 BIT ADDRESS NAME QUAL. (CR24.6) nCTS2 0 1 Table 67 - nDTR2 MUXING MUX CONTROL PIN 16 BIT ADDRESS ...
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MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) DRQ3 1 0 Table 72 - nDACK3 MUXING MUX CONTROL DMA3SEL PIN NAME (LD8:CRC0.1) nDACK3 1 0 UNCONNECTED SELECTED FUNCTION DRQ3 (default) P12 UNCONNECTED SELECTED FUNCTION nDACK3 (default) P16 155 STATE OF INPUTS - ...
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Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_TIME_OUT 0xF1 Default = 0x00 on Vcc POR or Reset_Drv WDT_VAL 0xF2 Default = 0x00 on Vcc POR or Reset_Drv WDT_CFG 0xF3 Default = ...
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Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08] NAME REG INDEX WDT_CTRL 0xF4 Default = 0x00 Cleared by VTR POR DEFINITION Watch-dog timer Control Bit[0] Watch-dog Status Bit, R timeout occurred =0 WD ...
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MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V Maximum V ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage IO8 Type Buffer Low Output Level High Output Level Output Leakage O8SR Type Buffer ...
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PARAMETER SYMBOL IO12 Type Buffer Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O24PD Type Buffer Low Output Level High Output Level Output Leakage O16SR Type Buffer Low Output ...
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PARAMETER SYMBOL OD24 Type Buffer Low Output Level Output Leakage OD48 Type Buffer Low Output Level Output Leakage ChiProtect (SLCT, PE, BUSY, nACK, nERROR) OD12 Type Buffer Low Output Level Output Leakage Backdrive (nSTROBE, nAUTOFD, nINIT, nSLCTIN) Backdrive (PD0-PD7) V ...
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A PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance CC LIMITS MIN TYP MAX OUT 162 UNIT TEST CONDITION pF All pins except pin under test tied ground ...
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For the Timing Diagrams shown, the following capacitive loads are used. NAME SD[0:7] IOCHRDY IRQ[3:7,10:12] DRQ[1:3] nWGATE nWDATA nHDSEL nDIR nSTEP nDS0 nMTR0 DRVDEN[1:0] TXD1 nRTS1 nDTR1 TXD2 nRTS2 nDTR2 PD[0:7] nSLCTIN nINIT nALF nSTB KDAT KCLK MDAT MCLK CAPACITANCE ...
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SAx SD<7:0> nIOW FIGURE 2 - IOW TIMING FOR PORT 92 NAME DESCRIPTION t1 SAx Valid to nIOW Asserted t2 SDATA Valid to nIOW Asserted t3 nIOW Asserted to SAx Invalid t4 nIOW Deasserted to DATA Invalid ...
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NAME DESCRIPTION t1 Vcc Slew from 4. Vcc Slew from 0V to 4.5V t3 All Host Accesses ...
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AEN SA[x], nCS t1 nIOW SD[x] FINTR PINTR IBF NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOW asserted t2 nIOW asserted to nIOW deasserted t3 nIOW asserted to SA[x], nCS invalid t4 SD[x] Valid to nIOW deasserted t5 ...
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AEN SA[x], nCS t1 nIOR SD[x] PD[x], nERROR, PE, SLCT, ACK, BUSY FINTER PINTER PCOBF AUXOBF1 nIOR/nIOW SEE TIMING PARAMETERS ON NEXT PAGE DATA VALID t9 t8 FIGURE 5 - ISA READ 167 t13 t6 t5 ...
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NAME DESCRIPTION t1 SA[x], nCS and AEN valid to nIOR asserted t2 nIOR asserted to nIOR deasserted t3 nIOR asserted to SA[x], nCS invalid t4 nIOR asserted to Data Valid t5 Data Hold/float from nIOR deasserted t6 nIOR deasserted t8 ...
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PCOBF AUXOBF1 nWRT IBF nRD FIGURE 6 - INTERNAL 8042 CPU TIMING NAME DESCRIPTION t1 nWRT deasserted to AUXOBF1 asserted (Notes 1,2) t2 nWRT deasserted to PCOBF asserted (Notes 1,3) t3 nRD deasserted to IBF deasserted (Note 1) Note 1: ...
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CLOCKI FIGURE 7A - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHz (Note) t2 Clock High Time/Low Time for 14.318MHz Clock Rise Time/Fall Time (not shown) Note: Tolerance is 0.01% RESET_DRV NAME DESCRIPTION t4 RESET width (Note) ...
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AEN FDRQ, PDRQ nDACK t14 nIOR or nIOW DATA (DO-D7) TC FIGURE 8A - DMA TIMING (SINGLE TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay ...
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AEN FDRQ, PDRQ t1 nDACK t14 t11 t6 t5 nIOR or nIOW DATA (DO-D7) TC FIGURE 8B - DMA TIMING (BURST TRANSFER MODE) NAME DESCRIPTION t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW ...
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MTR0-1 FIGURE 9 - DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx FIGURE 10 - SERIAL PORT TIMING NAME DESCRIPTION t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from ...
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PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK nPINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR FIGURE 11 - PARALLEL PORT TIMING NAME DESCRIPTION t1 PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW t2 PINTR Delay from ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR FIGURE 12A - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t12 ...
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NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWRITE to Command Asserted t4 nWAIT Deasserted to Command Deasserted (Note 1) t5 nWAIT Asserted to PDATA Invalid (Note 1) t6 Time Out ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB nWAIT FIGURE 13A - EPP 1.9 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t11 ...
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NAME DESCRIPTION t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted (Note 1) t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t6 PDATA Hi-Z to nWAIT Deasserted ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR FIGURE 14A - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t18 t9 t6 t19 t12 t11 ...
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NAME DESCRIPTION t1 nIOW Asserted to PDATA Valid t2 Command Deasserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted (Note 2) t5 Command Deasserted to PDATA Invalid t6 Time Out t8 SDATA Valid to nIOW ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR FIGURE 15A - EPP 1.7 DATA OR ADDRESS READ CYCLE SEE TIMING PARAMETERS ON NEXT PAGE t20 t15 t11 t13 t12 t10 t5 t2 182 t22 ...
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NAME DESCRIPTION t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 nIOR Asserted to IOCHRDY Asserted t10 nWAIT Deasserted to IOCHRDY Deasserted t11 IOCHRDY ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer ...
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Microsoft. The dynamic driver PDATA nSTROBE BUSY FIGURE 16 - PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 DATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 DATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active ...
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PDATA<7:0> nSTROBE t6 BUSY FIGURE 17 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PDATA<7:0> nACK nAUTOFD FIGURE 18 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted (Notes 1,2) t4 nACK Deasserted to nAUTOFD Asserted (Note ...
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DATA IRRX n IRRX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width ...
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DATA IRTX n IRTX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse ...
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DATA IRRX n IRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated ...
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DATA IRTX n IRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated ...
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TD/TE H 0.10 A1 -C- MIN MIN DIM A 2.80 3.15 .110 .124 0.1 0.45 .004 .018 A1 A2 2.57 2.87 .101 .113 D 23.4 24.15 .921 .951 ...
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PAGE SECTION/FIGURE/ENTRY 1 FEATURES 104 POWER MANAGEMENT/ VTR Support 110 Serial IRQ 112 IRQSER Data Frame 113 First Paragraph 127 SYSTEM MANAGEMENT INTERRUPT (SMI)/PME Support 133 Table 52/0xF4 (Hard Reset and VCC POR column) 135 Table 53/Chip Level, SMSC Defined ...
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ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...