FDC37M707-MS Standard Microsystems (SMSC), FDC37M707-MS Datasheet - Page 21

• Manufacturer Part Number: FDC37M707-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37M707-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset.
data
Configuration Control Register (CCR) not the
DSR, for PC/AT and PS/2 Model 30 and
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 Kbps after a
hardware reset.
BIT 2 through 4
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
precompensation values for the combination of
these bits settings.
starting track number to start precompensation.
this starting track number can be changed by
the configure command.
rate
RESET
COND.
See Table 11 for the settings
is
RESET
S/W
programmed
7
0
Track 0 is the default
PRECOMPENSATION
Table 10 shows the
POWER
DOWN
6
0
using
5
0
0
The
the
COMP2
PRE-
21
4
0
can set the data rate in the DSR. The data rate
of the floppy controller is the most recent write
of either the DSR or CCR. The DSR is
unaffected by a software reset.
reset
corresponds to the default precompensation
setting and 250 Kbps.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into manual low power mode. The
floppy controller clock and data mode after a
software reset or access to the Data Register or
Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
Note: The DSR is Shadowed in the Floppy Data
Rate Select Shadow Register, LD8:CRC2[7:0].
separator circuits will be turned off.
controller will come out of manual low power.
COMP1
PRE-
will
3
0
set
COMP0
PRE-
the
2
0
DSR
DRATE
SEL1
1
1
to
DRATE
SEL0
02H,
A hardware
0
0
which
The