W83627SF-AW Winbond, W83627SF-AW Datasheet
W83627SF-AW
Specifications of W83627SF-AW
Related parts for W83627SF-AW
W83627SF-AW Summary of contents
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... W83627SF WINBOND I W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... Table of Contents- 1. GENERAL DESCRIPTION ............................................................................................................ 6 2. FEATURES .................................................................................................................................... 7 3. PIN CONFIGURATION FOR W83627SF .................................................................................... 10 4. PIN DESCRIPTION...................................................................................................................... 11 4.1 LPC Interface ..................................................................................................................... 11 4.2 FDC Interface ..................................................................................................................... 12 4.3 Multi-Mode Parallel Port ..................................................................................................... 13 4.4 Serial Port Interface............................................................................................................ 18 4.5 KBC Interface ..................................................................................................................... 19 4.6 ACPI Interface .................................................................................................................... 19 4.7 Game Port & MIDI Port ...................................................................................................... 20 4.8 General Purpose I/O Port ...
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... ECP Register and Mode Definitions .....................................................................................53 8.3.2 Data and ecpAFifo Port ........................................................................................................54 8.3.3 Device Status Register (DSR)..............................................................................................54 8.3.4 Device Control Register (DCR) ............................................................................................55 8.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.........................................................................56 8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ..............................................................................56 Publication Release Date: May 31, 2005 - 3 - W83627SF Revision A1 ...
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... Interrupt Status Register (ISR, read only at "base address + 2") ..................................... 75 13.5 Smart Card FIFO Control Register (SCFR, write only at "base address + 2") ................. 76 13.6 Smart Card Control Register (SCCR, write only at "base address + 3") .......................... 77 13.7 Interrupt Enable Register (IER, at "base address + 4") .................................................... 77 -4- W83627SF ...
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... APPLICATION CIRCUITS ......................................................................................................... 112 17.1 Parallel Port Extension FDD ............................................................................................ 112 17.2 Parallel Port Extension 2FDD .......................................................................................... 113 17.3 Four FDD Mode................................................................................................................ 113 18. ORDERING INSTRUCTION ...................................................................................................... 114 19. HOW TO READ THE TOP MARKING....................................................................................... 114 20. PACKAGE DIMENSIONS .......................................................................................................... 115 21. REVISION HISTORY ................................................................................................................. 116 Publication Release Date: May 31, 2005 - 5 - W83627SF Revision A1 ...
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... TM Phoenix MultiKey/ customer code. The W83627SF provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. The W83627SF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide. ...
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... The W83627SF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices. They are very important for a entertainment or consumer computer. 2. FEATURES General Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (serial IRQ) ...
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... Support binary and BCD arithmetic 6 MHz, 8 MHz, 12 MHz MHz operating frequency Game Port Support two separate Joysticks Support every Joystick two axis (X,Y) and two button (A,B) controllers Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification TM -2, Phoenix MultiKey/42 -8- W83627SF 16 - customer code with ...
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... SMART Card Wake-up by SCPSNT On Now Wake-Up from all of the ACPI sleeping states (S1-S5) Smart Card Reader Interface PC/SC T=0, T=1 compliant ISO7816 protocol compliant With 16-byte send/receive FIFOs Programmable baud generator Package 128-pin PQFP Publication Release Date: May 31, 2005 - 9 - W83627SF Revision A1 ...
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... PIN CONFIGURATION FOR W83627SF 103 S5IN#/GP41 104 STRCTL/GP40 105 GP56/PVIDLIM1 106 GP55/VIDO4 107 GP54/VIDO3 108 GP53/VIDO2 109 GP52/VIDO1 110 GP51/VIDO0 111 GP50/PVIDLIM0 112 SCPSNT/GP74 113 SCIO/GP73 114 VCC 115 SCPWR/GP72/STGP72 116 SCCLK/GP71 117 VSS 118 SCRST#/GP70/STGP70 119 MSI/GP20 120 ...
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... These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. 32khz clock input, for CIR only. Publication Release Date: May 31, 2005 - 11 - W83627SF Revision A1 ...
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... Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input cs pin is pulled up internally can be disabled by bit 7 of L0-CRF0 (FIPURDWN). -12- W83627SF FUNCTION This input pin is pulled up This active low open drain output An open re sistor. The resistor ...
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... This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# 12 This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC W83627SF FUNCTION resistor. The resistor can FUNCTION Publication Release Date: May 31, 2005 Revision A1 ...
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... Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION. 2FDD MODE: MOA2# 12 This pin is for Extension FDD A; its function is the same as the MOA# pin of FDC. -14- W83627SF FUNCTION ...
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... WP# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: WP2# t This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC pulled high internally W83627SF FUNCTION Refer to the description of the It is pulled high Publication Release Date: May 31, 2005 Revision A1 ...
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... ECP and EPP mode. 12 EXTENSION FDD MODE: STEP2# This pin is for Extension FDD B; its function is the same as the STEP# pin of FDC. EXTENSION 2FDD MODE: STEP2# 12 This pin is for Extension FDD A and B; its function is the same as the STEP# pin of FDC. -16- W83627SF FUNCTION ...
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... An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. - EXTENSION FDD MODE: This pin is a tri-state output. - EXTENSION 2FDD MODE: This pin is a tri-state output W83627SF FUNCTION Publication Release Date: May 31, 2005 Revision A1 ...
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... UART A Serial Output used to transmit serial data out to 8t the communication link. During power-on reset, this pin is pulled down internally and is defined as PENKBC, which provides the power-on value for CR24 bit 2 (ENKBC). A 4.7 k resistor is recommended if intends to pull up. (enable KBC) -18- W83627SF FUNCTION is recommended if is recommended if ...
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... S5 state. This pin is pulse output, active low Panel Switch Input. This pin is high active with an internal pull down resistor. Battery voltage input W83627SF FUNCTION resistor is recommended if An active low signal indicates the FUNCTION FUNCTION Publication Release Date: May 31, 2005 Revision A1 ...
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... Alternate Function Output:KBC P14 I/O port. 12t Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. 12t Alternate Function Output:KBC P13 I/O port. 12t Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. 12t Alternate Function Output:KBC P12 I/O port. 12t -20- W83627SF FUNCTION ...
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... General purpose I/O port 3 bit 3. This pin generates the RSMRST signal while the VSB come in. (Default) General purpose I/O port 3 bit 2. This pin generates the PWROK signal while the VCC come in. (Default W83627SF FUNCTION FUNCTION Publication Release Date: May 31, 2005 Revision A1 ...
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... General purpose I/O port 7 bit 0. Power on setting pin for selecting functions of GP7. value is latched on the rising edge of POWEROK. This pin is internally pulled down during power on, a 4.7 k recommended if intends to pull up. Refer to detailed descrption of CR2C bit 6, 5. -22- W83627SF Setting resistor is Setting resistor is ...
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... CRFA in logical device C. General purpose I/O port 5 bit 5. Alternate VID output bit 4. General purpose I/O port 5 bit 4. Alternate VID output bit 3. General purpose I/O port 5 bit 3. Alternate VID output bit 2. Publication Release Date: May 31, 2005 - 23 - W83627SF Setting resistor is resistor is Revision A1 ...
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... Alternate VID input bit 0. Crystal input Dedicated power supply for oscillator. Crystal output 32KHz output clock. 2 +3.3V power supply for driving 3V on host interface. +5V power supply for the digital circuitry. +5V stand-by power supply for the digital circuitry. Ground. -24- W83627SF FUNCTION resistor is FUNCTION FUNCTION ...
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... Bit 1: ETBREI. Setting this bit to a logical 1 enables TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables RBR data ready interrupt Enable RBR Data Ready Interrupt (ERDRI) Enable TBR Empty Interrupt (ETBREI) Enable SSR Interrupt (ESSRI) Enabel SCPSNT Interrupt (ESCPTI W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... Ready level reached Data present in RX FIFO Data FIFO for 4 characters Timeout period of time since last access of RX FIFO. TBR Empty TBR empty -26- W83627SF CLEAR INTERRUPT - 2. PBER =1 Read SCSR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1 ...
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... Transmitter FIFO reset RX interrupt active level (LSB) RX interrupt active level (MSB) FIFO TRIGGER LEVEL RX FIFO INTERRUPT ACTIVE LEVEL (BYTES Parity Bit Enable (PBE) Even Parity Enable (EPE) Baud rate Divisor Latch Access Bit (BDLAB W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... FIFO cleared by reading SCSR until there are no remaining errors left in the FIFO IRQ enable RBR Data Ready (RDR) Overrun Error (OER) Parity Bit Error (PBER) No Stop bit Error (NSER) Silent Byte Detected (SBD) Transmitter Buffer Register Empty (TBRE) Transmitter Shift Register Empty (TSRE) RX FIFO Error Indication (RFEI) -28- W83627SF ...
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... Bit 5 – 4: These two bits (CLKSEL1 and CLKSEL0 respectively) select frequency of SCCLK Warm reset SCIO direction CLKSTP CLKSTPH SCCLK frequency select bit 0 SCCLK frequency select bit 1 Internal sampling clock base select bit 0 Internal sampling clock base select bit W83627SF MULTIPLIER 14x 16x 18x 16x Publication Release Date: May 31, 2005 Revision A1 ...
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... ENABLE (ETBREI) (EUSRI) Interrupt Interrupt Interrupt Status Status Status Bit (0) Bit (1) Bit (2) RCVR XMIT FIFO FIFO Reserved Reserved Reversed Reset Reset -30- W83627SF SCCLK FREQUUENCY 1.5 MHz 3 MHz 6 MHz 12 MHz Data RX Data RX Data RX Data Bit 4 Bit 5 Bit 6 TX Data TX Data TX Data TX Data ...
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... Parity Bit No Stop Data Error Error Bit Error (OER) (PBER) (NSER) SCIO CLKSTP CLKSTPH reset direction Bit 0 Bit 1 Bit 2 Bit 3 Bit 8 Bit 9 Bit 10 Bit W83627SF Baudrate Even Divisor Parity 0 0 Enable Access Bit (EPE) (BDLAB SILENT RX FIFO TBR TSR BYTE Empty ...
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... Interrupt Interrupt Interrupt "0" if Status Status Status Interrupt Pending Bit (0) Bit (1) Bit (2)** RCVR XMIT DMA FIFO FIFO FIFO Mode Enable Reset Reset Select -32- W83627SF Data RX Data RX Data Bit 4 Bit 5 Bit 6 TX Data TX Data TX Data Bit 4 Bit 5 Bit FIFOs 0 0 Enabled ** ...
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... RI Falling DCD Toggling Toggling Edge Toggling (TCTS) (TDSR) (FERI) (TDCD) Bit 0 Bit 1 Bit 2 Bit 3 Bit 0 Bit 1 Bit 2 Bit 3 Bit 8 Bit 9 Bit 10 Bit W83627SF Even Parity Set Parity Bit Fixed Silence Enable Enable Enable (EPE) PBFE) (SSE) Internal Loopback 0 0 Enable Silent ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) -34- W83627SF DATA LENGTH 5 bits 6 bits 7 bits 8 bits ...
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... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS , Loopback RI input ( bit 2 of HCR) DCD . - 35 - W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) -36- W83627SF ...
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... UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB) TABLE 6-3 FIFO TRIGGER LEVEL RX FIFO INTERRUPT ACTIVE LEVEL (BYTES W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... FIFO Data 4 characters period of time Timeout since last access of RX FIFO. TBR Empty TBR empty 1. TCTS = 1 Handshake status 3. FERI = 1 -38- W83627SF 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled CLEAR INTERRUPT - 2. PBER =1 Read USR 1 ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI W83627SF 16 -1. The output frequency of Publication Release Date: May 31, 2005 Revision A1 ...
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... USED TO GENERATE 24M HZ 16X CLOCK 650 2304 975 1536 1430 1047 1478.5 857 1950 768 3900 384 7800 192 15600 96 23400 64 26000 58 31200 48 46800 32 62400 24 93600 16 124800 12 249600 6 499200 3 748800 2 1497600 1 -40- W83627SF ERROR PERCENTAGE BETWEEN DESIRED AND ACTUAL ** ** 0.18% 0.099 0.53 ...
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... Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR. Publication Release Date: May 31, 2005 - 41 - W83627SF Revision A1 ...
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... Receiver Frequency Range 2~0. These bits select the input frequency of the receiver ranges. For the input signal, that is through a band pass filter, i.e., the frequency of the input signal is located at this defined range then the signal will be received. Receiver Frequency Select 4~0. Select the receiver operation frequency. -42- W83627SF ...
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... Received FIFO overrun. Read to clear. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical W83627SF 011 MIN. MAX. 23.4 34.2 25 ...
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... Baud Rate Pre-divisor. Set to 1, the baud rate generator input clock is set to 1.8432M Hz which is set to pre- divisor into 13. When set to 0, the pre-divisor is set to 1, that is, the input clock of baud rate generator is set to 24M Hz. Receiving Signal Invert. Write to 1, Invert the receiving signal. -44- W83627SF internal decoder ...
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... FIFO level value and successively read RBR by the prior value. TABLE: BAUD RATE TABLE GENERATE 16X CLOCK 2304 1536 1047 857 768 384 192 W83627SF DESCRIPTION PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL ** ** 0.18% 0.099 0.53% ** Publication Release Date: May 31, 2005 ...
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... EN_TMR (Enable Timer) of Bank0.Reg2. is set to 1. When the timer down count to zero and EN_TMR=1, the TMR_I is set to 1. When the counter down count to zero, a new initial value will be re-loaded into timer counter. -46- W83627SF PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL ** ** ** ...
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... Printer Interface Logic The parallel port of the W83627SF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83627SF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... TABLE 8-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER CONNECTOR OF W83627SF ATTRIBUTE 8.2 Enhanced Parallel Port (EPP) TABLE 8-2 PRINTER MODE AND EPP REGISTER ADDRESS Notes: 1. These registers are available in all modes. 2. These registers are available only in EPP mode. ...
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... Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows TMOUT ERROR SLCT PE ACK BUSY ACK# BUSY# stops W83627SF signal means the printer has Publication Release Date: May 31, 2005 Revision A1 ...
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... CPU STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR ACK auses an EPP address write cycle to be performed, and the -50- W83627SF changes from low to high. 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ...
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... SLIN PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 - 51 - W83627SF PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 IOR# causes an EPP read PD2 PD1 PD0 1 1 TMOUT INIT# AUTOFD# ...
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... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. EPP DESCRIPTION -52- W83627SF ...
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... R/W 110 R 111 R/W 111 R/W All DESCRIPTION Publication Release Date: May 31, 2005 - 53 - W83627SF FUNCTION Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register ...
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... Device Status Register (DSR) These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows -54- W83627SF 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE 1 nFault Select PError nAck nBusy ...
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... The printer is selected. Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output W83627SF strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: May 31, 2005 Revision A1 ...
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... Bit 7: This bit is read-only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. Bit 5-3: Reflect the IRQ resource assigned for ECP port -56- W83627SF IRQx 0 IRQx 1 IRQx 2 intrValue compress ...
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... Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. IRQ RESOURCE reflect other IRQ resources selected by PnP register (default) IRQ7 IRQ9 IRQ10 IRQ11 IRQ14 IRQ15 IRQ5 W83627SF . empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: May 31, 2005 Revision A1 ...
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... These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 Address or RLE field PError Select nFault Directio ackIntEn SelectIn Parallel Port Data FIFO ECP Data FIFO Test FIFO nErrIntrEn dmaEn -58- W83627SF NOTE PD2 PD1 PD0 nInit autofd strobe serviceIntr full ...
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... ECP Mode. This signal sets the transfer direction (asserted = reverse, O deasserted = forward). This pin is driven low to place the channel in the reverse direction. O This signal is always deasserted in ECP mode W83627SF DESCRIPTION Publication Release Date: May 31, 2005 Revision A1 ...
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... PeriphAck is low. The most significant bit of the command is always zero. 8.3.13.3 Data Compression The W83627SF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... Extension FDD Mode (EXTFDD) In this mode, the W83627SF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 8-1-2. ...
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... KEYBOARD CONTROLLER The KBC (8042 with licensed KB BIOS) circuit of W83627SF is designed to provide the functions needed to interface a CPU with a keyboard and/or a PS/2 mouse, and can be used with IBM compatible personal computers or PS/2-based systems. The controller receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer ...
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... It defaults to 0 after a power-on reset. 0: Data byte 1: Command byte 0: Keyboard is inhibited 1: Keyboard is not inhibited 0: Auxiliary device output buffer empty 1: Auxiliary device output buffer full 0: No time-out error 1: Time-out error 0: Odd parity 1: Even parity (error) Publication Release Date: May 31, 2005 - 63 - W83627SF Revision A1 ...
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... A9h Self-test AAh Returns 055h if self test succeeds FUNCTION BIT BIT DEFINITION 00 No Error Detected 01 Auxiliary Device "Clock" line is stuck low 02 Auxiliary Device "Clock" line is stuck high Auxiliary Device "Data" line is stuck low 03 04 Auxiliary Device "Data" line is stuck low -64- W83627SF ...
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... Pulse only RC(the reset line) low for Command byte is even FUNCTION BIT DEFINITION BIT No Error Detected 00 01 Keyboard "Clock" line is stuck low 02 Keyboard "Clock" line is stuck high Keyboard "Data" line is stuck low 03 04 Keyboard "Data" line is stuck high Publication Release Date: May 31, 2005 - 65 - W83627SF Revision A1 ...
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... A "0" on this bit drives GATE A20 signal to low. PLKBRST (Pull-Low KBRESET) A "1" on this bit causes KBRESET to drive low for 6 S(Min.) with 14 S(Min.) delay. Before issuing another keyboard reset command, the bit must be cleared Res. (1) Res. (0) Res. (0) -66- W83627SF P92EN HGA20 HKBRST Res. (1) SGA20 PLKBRST ...
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... GENERAL PURPOSE I/O W83627SF provides 42 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. These 42 GP I/O ports are divided into seven groups. GP1 is configured through control registers in logical device 7, GP2 in logical device 8, GP3 and GP4 in logical device 9, GP5, GP6, and GP7 in logical device C ...
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... BIT 2 BIT 3 BIT 4 BIT 5 BIT 0 BIT 1 BIT 2 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 0 BIT 1 BIT 2 BIT 3 -68- W83627SF GP I/O PORT GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 GP30 GP31 GP32 GP33 GP34 GP35 GP40 GP41 GP42 GP50 ...
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... PLUG AND PLAY CONFIGURATION The W83627SF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83627SF, there are twelve Logical Devices (from Logical Device 0 to Logical Device C with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART A ...
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... The designer can also set bit 5 of CR26 (LOCKREG) to high to protect the configuration registers against accidental accesses. The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers. ADDRESS AND VALUE -70- W83627SF ...
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... Extended Functions Enable Registers (EFERs) After a power-on reset, the W83627SF enters the default operating mode. Before the W83627SF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
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... Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------- MOVDX,2EH MOVAL,07H OUTDX,AL ; point to Logical Device Number Reg. MOVDX,2FH MOVAL,01H OUTDX,AL ; select logical device 1 ; MOVDX,2EH MOVAL,F0H OUTDX,AL ; select CRF0 MOVDX,2FH MOV AL,3CH OUTDX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode ;------------------------------------------ MOVDX,2EH MOV AL,AAH OUTDX,AL | -72- W83627SF | ...
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... ACPI REGISTERS FEATURES W83627SF supports both ACPI and legacy power managements. The switch logic of the power management block generates an SMI# interrupt in the legacy mode and an PME# interrupt in the ACPI mode. The new ACPI feature routes SMI# / PME# logic output either to SMI PME# .The SMI# / PME# logic routes to SMI# only when both PME_EN = 0 and SMIPME_OE = 1 ...
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... Bit 1: ETBREI. Setting this bit to a logical 1 enables TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables RBR data ready interrupt Enable RBR Data Ready Interrupt (ERDRI) Enable TBR Empty Interrupt (ETBREI) Enable SSR Interrupt (ESSRI) Enabel SCPSNT Interrupt (ESCPTI) -74- W83627SF ...
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... Data present in RX FIFO for 4 characters FIFO Data Timeout period of time since last access of RX FIFO. TBR Empty TBR empty - 75 - W83627SF CLEAR INTERRUPT SOURCE - 2. PBER =1 Read SCSR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1 ...
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... Bit 0: This bit enables FIFO of Smart Card interface. This bit should be set to a logical 1 before other bits of SCFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset RX interrupt active level (LSB) RX interrupt active level (MSB) FIFO TRIGGER LEVEL RX FIFO INTERRUPT ACTIVE LEVEL (BYTES) -76- W83627SF ...
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... Bit 3: The Smart Card interface interrupt output is enabled by setting this bit to a logic 1. Bit 2 – 0: Reserved. Always 0 when read Parity Bit Enable (PBE) Even Parity Enable (EPE) Baud rate Divisor Latch Access Bit (BDLAB IRQ enable - 77 - W83627SF Publication Release Date: May 31, 2005 Revision A1 ...
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... RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical RBR Data Ready (RDR) Overrun Error (OER) Parity Bit Error (PBER) No Stop bit Error (NSER) Silent Byte Detected (SBD) Transmitter Buffer Register Empty (TBRE) Transmitter Shift Register Empty (TSRE) RX FIFO Error Indication (RFEI) -78- W83627SF ...
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... Warm reset SCIO direction CLKSTP CLKSTPH SCCLK frequency select bit 0 SCCLK frequency select bit 1 Internal sampling clock base select bit 0 Internal sampling clock base select bit W83627SF MULTIPLIER 14x 16x 18x 16x SCCLK FREQUUENCY 1.5 MHz 3 MHz 6 MHz 12 MHz Publication Release Date: May 31, 2005 ...
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... Reset Reset Parity Bit 1 0 Enable (PBE) IRQ 0 0 Enable No Stop Overrun Parity Bit Bit Error Error Error (OER) (PBER) (NSER) -80- W83627SF Data RX Data RX Data Bit 4 Bit 5 Bit 6 TX Data TX Data TX Data Bit 4 Bit 5 Bit 6 SCPSNT toggle interrupt 0 0 Enable (ESCPTI) ...
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... High 14. SERIAL IRQ W83627SF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame ...
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... Frame is low for 3 clocks, the next IRQSER cycle's Sample mode is the Continuous mode. Table 14-2 IRQSER Sampling periods SIGNAL SAMPLED IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned -82- W83627SF # OF CLOCKS PAST START ...
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... PRTPWD. Printer port power down enable Power down = 1 No Power down Bit 2 : Reserved. Bit 1 : SCPWD. Smart card interface power down enable Power down = 1 No Power down Bit 0 : FDCPWD. FDC power down enable Power down = 1 No Power down Publication Release Date: May 31, 2005 - 83 - W83627SF Revision A1 ...
Page 84
... This register contains enable bit for tri-state device's output pins when corresponding power down enable bit (specified in CR24) is set. Bit Reserved Bit 5 : URBTRI. For UART B device. Bit 4 : URATRI. For UART A device. Bit 3 : PRTTRI. For printer port device. Bit 2 : Reserved. Bit 1 : SCTRI. For Smart Card interface. Bit 0 : FDCTRI. For FDC device. -84- W83627SF ...
Page 85
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ. Publication Release Date: May 31, 2005 - 85 - W83627SF Revision A1 ...
Page 86
... SLP_SX# (pin 73) signal falling edge. Then it is reset by the falling edge of S5# signal (pin 103). *Note: The falling edge of PWRCTL# signal (pin 72) is delayed an additional 5ms from the falling edge of SLP_SX# signal for supporting STR (Suspend To RAM) function. -86- W83627SF ...
Page 87
... CR2B (GPIO multiplexed pin selection register 2. VCC powered. Default 0xC0) Bit Reserved Bit 5 : PIN90S = 0PLED (PLED0 control bits are in CRF5 bit Logical Device 8) = 1GP23 Bit 4 : PIN89S = 0 WDTO (Watch Dog Timer is controlled by CRF5, CRF6, CRF7 of Logical Device GP24 Bit 3 : PIN88S = 0 IRRX = 1 GP25 Publication Release Date: May 31, 2005 - 87 - W83627SF Revision A1 ...
Page 88
... GP function initially and switch to Smard Card function. Bit 4-0 : Reserved CR2D (Default 0x00) Test Mode: Reserved for Winbond. CR2E (Default 0x00) Test Mode: Reserved for Winbond. CR2F (Default 0x00) Test Mode: Reserved for Winbond. VID function. -88- W83627SF ...
Page 89
... When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. Bit 4 : Swap Drive 0, 1 Mode = 0 No Swap (Default Drive and Motor sel 0 and 1 are swapped. Bit :Interface Mode = 11 AT Mode (Default (Reserved PS Model 30 Publication Release Date: May 31, 2005 - 89 - W83627SF Revision A1 ...
Page 90
... Disable FDD write(forces pins WE, WD stay high). Bit 0 : SWWP = 0 Normal, use WP to determine whether the FDD is write protected or not FDD is always write-protected. CRF2 (Default 0xFF) Bit FDD D Drive Type Bit FDD C Drive Type Bit FDD B Drive Type Bit FDD A Drive Type -90- W83627SF ...
Page 91
... W83627SF SELDEN FM --- 1 250K 1 150K 0 125K 0 --- 1 250K 1 250K 0 125K 0 --- 1 250K 1 --- 0 125K 0 Publication Release Date: May 31, 2005 Revision A1 ...
Page 92
... Bit These bits select DRQ resource for Parallel Port. 0x00=DMA0 0x01=DMA1 0x02=DMA2 0x03=DMA3 0x04 - 0x07= No DMA active TABLE B DRVDEN1(PIN 3) SELDEN DRATE0 DRATE1 DRATE0 DRATE0 SELDEN DRATE0 DRATE1 -92- W83627SF DRIVE TYPE 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) ...
Page 93
... CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise) These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. Publication Release Date: May 31, 2005 - 93 - W83627SF Revision A1 ...
Page 94
... Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock -94- W83627SF IRRX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX ...
Page 95
... Select 6MHz as KBC clock input Select 8MHz as KBC clock input Select 12Mhz as KBC clock input Select 16Mhz as KBC clock input. (W83627SF/W83627HF/F-AW can support these 4 kinds of clock input, but W83627SF/ W83627HF/F-PW only support 12MHz clock input) Bit Reserved. Bit Port 92 disable. ...
Page 96
... CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for MIDI Port . CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. -96- W83627SF ...
Page 97
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP20-GP27 inversion register. Default 0x00) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. RX FIFO INTERRUPT ACTIVE LEVEL (BYTES Publication Release Date: May 31, 2005 - 97 - W83627SF Revision A1 ...
Page 98
... Time-out occurs after 255 second/minutes note: The corresponding power on setting pin is pin 81 and its value is latched on the rising edge of PWROK. 1: CRF6 is initialized to be 0x0A and CR30 of this logical device is initialized to be 0x01. 0: CRF6 is initialized to be 0x00 and CR30 of this logical device is initialized to be 0x00. -98- W83627SF ...
Page 99
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP30-GP35 inversion register. Default 0x00 Bit Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: May 31, 2005 - 99 - W83627SF Revision A1 ...
Page 100
... ENMSWAKEUP. Enable Mouse to wake-up system via PANSW_OUT. = 0Disable Mouse wake-up function. = 1Enable Mouse wake-up function. Bit 4 : MSRKEY. Select Mouse Left/Right Button to wake-up system via PANSW_OUT. = 0Select click on Mouse Left-button twice to wake the system up. = 1Select click on Mouse right-button twice to wake the system up. -100- W83627SF ...
Page 101
... Bit 1 : Mouse_STS. The Panel switch event is caused by Mouse wake-up event. This bit is cleared by reading this register. Bit 0 : Keyboard_STS. The Panel switch event is caused by Keyboard wake-up event. This bit is cleared by reading this register. Publication Release Date: May 31, 2005 - 101 - W83627SF Revision A1 ...
Page 102
... ENMDATUP: Enable an MDAT low pulse to wake up system through PSOUT#. = 0Disable. = 1Enable. Bit 6 : EN_SCUP: Enable SCPSNT# of Smart Card interface to wake up system through PSOUT#. = 0Disable. = 1Enable. Bit CIR Baud Rate Divisor. The clock base of CIR is 32k Hz, so that the baud rate is 32khz divided by (CIR Baud Rate Divisor + 1). -102- W83627SF ...
Page 103
... Bit 5 : MIDIPME. MIDI port auto power management enable disable the auto power management functions = 1 enable the auto power management functions. Publication Release Date: May 31, 2005 - 103 - W83627SF Revision A1 ...
Page 104
... Writing a 0 has no effect. Bit 5 : MOUIRQSTS. MOUSE IRQ status. Bit 4 : KBCIRQSTS. KBC IRQ status. Bit 3 : PRTIRQSTS. printer port IRQ status. Bit 2 : FDCIRQSTS. FDC IRQ status. Bit 1 : URAIRQSTS. UART A IRQ status. Bit 0 : URBIRQSTS. UART B IRQ status. -104- W83627SF ...
Page 105
... SMI / PME interrupt due to UART A's IRQ. Bit 0 : URBIRQEN. = 0disable the generation of an SMI / PME interrupt due to UART B's IRQ. = 1enable the generation of an SMI / PME interrupt due to UART B's IRQ. Publication Release Date: May 31, 2005 - 105 - W83627SF Revision A1 ...
Page 106
... FSLEEP: This bit selects the fast expiry time of individual devices second milli-seconds. Bit 0 : SMIPME_OE: This is the SMI and PME output enable bit neither SMI nor PME will be generated. Only the IRQ status bit is set SMI or PME event will be generated. CRFE, FF (Default 0x00) Reserved for Winbond test. -106- W83627SF ...
Page 107
... If a port is programmed input port, then its respective bit can only be read. CRF2 (GP50-GP56 inversion register. Default 0x00 Bit 7: Reserved) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. Publication Release Date: May 31, 2005 - 107 - W83627SF Revision A1 ...
Page 108
... VID code table. = 1new VID code table. Bit 6 – VID guarding bits. The corresponding power on setting pins are GP56, 66 and their values are latched on the rising edge of PWROK signal. BIT 6 BIT -108- W83627SF LIMIT No constraint 3 units constraint 4 units constraint 5 units constraint ...
Page 109
... V DD 2.2 to 4.0 BAT 0 to +70 -55 to +150 10 0V) SS SYM. MIN. TYP. MAX. I 2.4 BAT I 2.0 BAT +10 LIH I -10 LIL - 109 - W83627SF UNIT V +0 UNIT CONDITIONS 2.5 V BAT V = 5.0 V, All ACPI SB mA pins are not connected Publication Release Date: May 31, 2005 ...
Page 110
... Output Low Voltage Output High Voltage SYM. MIN. TYP. MAX +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL +10 LIH I -10 LIL V 0 2.4 OH -110- W83627SF UNIT CONDITIONS - - ...
Page 111
... Voltage Hystersis SYM. MIN. TYP. MAX +10 LIH I -10 LIL 0 2 +10 LIH I -10 LIL V 1.3 1.5 1 3.2 3 +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 111 - W83627SF UNIT CONDITIONS - Publication Release Date: May 31, 2005 Revision A1 ...
Page 112
... IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram SYM. MIN. TYP. MAX. I +10 LIH I -10 LIL V 0.5 0.8 1 1.6 2.0 2 0.5 1 +10 LIH I -10 LIL JP13 -112- W83627SF UNIT CONDITIONS 13A DCH2 34 33 HEAD2 32 31 ...
Page 113
... Parallel Port Extension 2FDD Connection Diagram 17.3 Four FDD Mode W83977F DSA DSB MOA MOB JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 113 - W83627SF JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 ...
Page 114
... W83627SF-AW © AM. MEGA. 87-96 101A5BCSA 1st line: Winbond logo & S 2nd line: the type number: W83627SF-AW 3rd line: the source of KBC F/W -- American Megatrends Incorporated 4th line: the tracking code packages made in 2001, week assembly house ID; A means ASE, S means SPIL, G means GR, etc. ...
Page 115
... QFP 102 65 103 128 See Detail F y Seating Plane Detail F - 115 - W83627SF Dimension in mm Dimension in inch Symbol Min Nom Max Min Nom A 0.25 0.35 0.45 0.010 0.014 1 A 2.57 2.72 2.87 0.101 0.107 2 b 0.004 0.008 0.10 0.20 0.30 c 0.10 ...
Page 116
... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 -116- W83627SF DESCRIPTION First published New composition IO MART@ ADD Important Notice Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China ...